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sharc and the sharc logo are registered trademarks of ana log devices, inc. sharc processors adsp-21367/adsp-21368/adsp-21369 rev. e information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the proper ty of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106 u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2009 analog devices, inc. all rights reserved. summary high performance 32-bit/40-bi t floating-point processor optimized for high performance audio processing single-instruction, multiple-data (simd) computational architecture on-chip memory2m bits of on-chip sram and 6m bits of on-chip mask programmable rom code compatible with all other members of the sharc family the adsp-21367/adsp-21368/adsp-21369 are available with a 400 mhz core instruction rate with unique audiocen- tric peripherals such as the di gital applications interface, s/pdif transceiver, serial ports, 8-channel asynchronous sample rate converter, precision clock generators, and more. for complete ordering information, see ordering guide on page 58 . dedicated audio components s/pdif-compatible digital audio receiver/transmitter 4 independent asynchronous sample rate converters (src) 16 pwm outputs configured as four groups of four outputs rom-based security features include jtag access to memory permitted with a 64-bit key protected memory regions that can be assigned to limit access under program cont rol to sensitive code pll has a wide variety of software and hardware multi- plier/divider ratios available in 256-ball bga_ed and 208-lead lqfp_ep packages figure 1. function al block diagram internal memory i/f block 0 ram/rom b0d 64-bit instruction cache 5 stage sequencer pex pey pmd 64-bit iod0 32-bit epd bus 32-bit core bus cross bar dai routing/pins s/pdif tx/rx pcg a - d dpi routing/pins spi/b uart 1 - 0 block 1 ram/rom block 2 ram block 3 ram ami sdram ep external port pin mux timer 2 - 0 sport 7 - 0 asrc 3 - 0 pwm 3 - 0 dag1/2 timer idp/ pdap 7 - 0 twi iod0 bus mtm pcg c - d peripheral bus 32-bit core flags flagx/irqx/ tmrexp jtag internal memory dmd 64-bit pmd 64-bit dmd 64-bit core flags iod1 32-bit peripheral bus b1d 64-bit b2d 64-bit b3d 64-bit dpi peripherals dai per ipherals pe ripherals external port simd core s
rev. e | page 2 of 60 | july 2009 adsp-21367/adsp-21368/adsp-21369 table of contents summary ............................................................... 1 dedicated audio components .................................... 1 general description ................................................. 3 sharc family core architecture ............................ 4 family peripheral architecture ................................ 7 i/o processor features ......................................... 10 system design .................................................... 10 development tools ............................................. 11 additional information ........................................ 12 pin function descriptions ....................................... 13 specifications ........................................................ 16 operating conditions .......................................... 16 electrical characteristics ....................................... 17 package information ........................................... 18 esd caution ...................................................... 18 maximum power dissipation ................................. 18 absolute maximum ratings ................................... 18 timing specifications ........................................... 18 output drive currents ......................................... 48 test conditions .................................................. 48 capacitive loading .............................................. 48 thermal characteristics ........................................ 50 256-ball bga_ed pinout ......................................... 51 208-lead lqfp_ep pinout ....................................... 54 package dimensions ............................................... 56 surface-mount design .......................................... 57 automotive products .............................................. 58 ordering guide ..................................................... 58 revision history 7/09rev. d to rev. e corrected all outstanding document errata. also replaced core clock references (cclk) in th e timing specifications with peripheral clock references (pclk). revised functional block diagram ................................1 added context switch ...............................................5 added universal registers ..........................................5 clarified vco operations. see voltage controlled oscillator .................................... 18 corrected the pins names for the dai and dpi in 256-ball bga_ed pinout ... ...................................... 51 208-lead lqfp_ep pinout . ...................................... 54 added 366 mhz lqfp epad mode ls for the adsp-21367 and adsp-21369. for additional spec ifications for these models, refer to the following: specifications ......................................................... 16 clock input ........................................................... 21 sdram interface timing (166 mhz sdclk) ............... 28 serial ports ............................................................ 34 ordering guide ...................................................... 58
adsp-21367/adsp-21368/adsp-21369 rev. e | page 3 of 60 | july 2009 general description the adsp-21367/adsp-21368/adsp-21369 sharc ? proces- sors are members of the simd sharc family of dsps that feature analog devices super harvard architecture. these pro- cessors are source code-compati ble with the adsp-2126x and adsp-2116x dsps as well as with first generation adsp-2106x sharc processors in sisd (single-instruction, single-data) mode. the processors are 32-bit/40-bit floating-point proces- sors optimized for high performance automotive audio applications with its large on -chip sram, mask programmable rom, multiple internal buses to eliminate i/o bottlenecks, and an innovative digital applications interface (dai). as shown in the functional block diagram on page 1 , the processors use two computational units to deliver a significant performance increase over the pr evious sharc processors on a range of dsp algorithms. fabricated in a state-of-the-art, high speed, cmos process, the adsp-21367/adsp-21368/ adsp-21369 processors achieve an instruction cycle time of up to 2.5 ns at 400 mhz. with it s simd computational hardware, the processors can perform 2. 4 gflops running at 400 mhz. table 1 shows performance benchm arks for these devices. the diagram on page 1 shows the two clock domains that make up the adsp-21367/adsp-21368/ adsp-21369 processors. the core clock domain contains the following features. ? two processing elements (p ex, pey), each of which com- prises an alu, multiplier, shifter, and data register file ? data address generators (dag1, dag2) ? program sequencer wi th instruction cache ? pm and dm buses capable of supporting 2x64-bit data transfers between me mory and the core at every core pro- cessor cycle ? one periodic interval timer with pinout ?on-chip sram (2m bit) ?on-chip mask-progr ammable rom (6m bit) ? jtag test access port for em ulation and boundary scan. the jtag provides software debug through user break- points which allows flex ible exception handling. table 1. processor benchmarks (at 400 mhz) benchmark algorithm speed (at 400 mhz) 1024 point complex fft (radix 4, with reversal) 23.2 s fir filter (per tap) 1 1 assumes two files in multichannel simd mode. 1.25 ns iir filter (per biquad) 1 5.0 ns matrix multiply (pipelined) [33] [31] [44] [41] 11.25 ns 20.0 ns divide (y/x) 8.75 ns inverse square root 13.5 ns table 2. adsp-2136x family features 1 feature adsp-21367 adsp-21368 adsp-21369/ adsp-21369w frequency 400 mhz ram 2m bits rom 2 6m bits audio decoders in rom yes pulse-width modulation yes s/pdif yes sdram memory bus width 32/16 bits serial ports 8 idp yes dai yes uart 2 dai and dpi yes s/pdif transceiver 1 ami interface bus width 32/16/8 bits spi 2 twi yes src performance 128 db package 256 ball- bga, 208-lead lqfp_ep 256 ball- bga 256 ball- bga, 208-lead lqfp_ep 1 w = automotive grade product. see automotive products on page 58 for more information. 2 audio decoding algorithms include pcm, dolby digital ex, dolby prologic iix, dts 96/24, neo:6, dts es, mpeg-2 aac, mp3, and functions like bass management, delay, speake r equalization, graphic equalization, and more. decoder/post-processor algo rithm combination support varies depending upon the chip version and the system configurations. please visit www.analog.com for complete information. table 2. adsp-2136x family features 1 (continued) feature adsp-21367 adsp-21368 adsp-21369/ adsp-21369w
rev. e | page 4 of 60 | july 2009 adsp-21367/adsp-21368/adsp-21369 the block diagram of the adsp-21368 on page 1 also shows the peripheral clock domain (also known as the i/o processor) and contains the following features: ?iod0 (peripheral dma) and iod1 (external port dma) buses for 32-bit data transfers ? peripheral and external port buses for core connection ? external port with an ami and sdram controller ?4 units for pwm control ? 1 mtm unit for internal-to- internal memory transfers ? digital applications interface that includes four precision clock generators (pcg), a input data port (idp) for serial and parallel interconnect, an s/pdif receiver/transmitter, four asynchronous sample rate converters, eight serial ports, a flexible signal routing unit (dai sru). ? digital peripheral interface th at includes three timers, a 2- wire interface, two uarts, two serial peripheral interfaces (spi), 2 precision clock generators (pcg) and a flexible sig- nal routing unit (dpi sru). sharc family core architecture the adsp-21367/adsp-21368/adsp -21369 are code compati- ble at the assembly level wi th the adsp-2126x, adsp-21160, and adsp-21161, and with the first generation adsp-2106x sharc processors. the adsp-21367/adsp-21368/ adsp-21369 processors share architectural features with the adsp-2126x and adsp-2116x si md sharc processors, as shown in figure 2 and detailed in the following sections. figure 2. sharc core block diadram s s s s ss ss s s s s s ss s s ss s s s ss
adsp-21367/adsp-21368/adsp-21369 rev. e | page 5 of 60 | july 2009 simd computational engine the processors contain two comp utational processing elements that operate as a single-instruction, multiple-data (simd) engine. the processing elements are referred to as pex and pey and each contains an alu, multiplier, shifter, and register file. pex is always active, and pey may be enabled by setting the peyen mode bit in the mode1 register. when this mode is enabled, the same instruction is executed in both processing ele- ments, but each processing elem ent operates on different data. this architecture is efficient at executing math intensive dsp algorithms. entering simd mode also has an effect on the way data is trans- ferred between memory and the processing elements. when in simd mode, twice the data bandwidth is required to sustain computational operation in the processing elements. because of this requirement, entering simd mode also doubles the band- width between memory and the processing elements. when using the dags to transfer data in simd mode, two data values are transferred with ea ch access of memory or the register file. independent, paralle l computation units within each processing element is a set of computational units. the computational units consist of an arithmetic/logic unit (alu), multiplier, and shifter. these units perform all opera- tions in a single cycle. the thre e units within each processing element are arranged in paralle l, maximizing computational throughput. single multifunctio n instructions execute parallel alu and multiplier operations . in simd mode, the parallel alu and multiplier operations occur in both processing elements. these computation un its support ieee 32-bit single- precision floating-point, 40-bit extended precision floating- point, and 32-bit fixed-point data formats. data register file a general-purpose data register file is contained in each pro- cessing element. the register fi les transfer data between the computation units and the data buses, and store intermediate results. these 10-port, 32-regist er (16 primary, 16 secondary) register files, combined with the adsp-2136x enhanced har- vard architecture, allow unco nstrained data flow between computation units and internal memory. the registers in pex are referred to as r0Cr15 and in pey as s0Cs15. context switch many of the processors register s have secondary registers that can be activated during interrupt servicing for a fast context switch. the data regist ers in the register file, the dag registers, and the multiplier resu lt registers all have secondary registers. the primary registers are active at reset, while the secondary registers are activated by control bits in a mode control register. universal registers these registers can be used for general-purpose tasks. the ustat (4) registers allow easy bit manipulations (set, clear, toggle, test, xor) for all system registers (control/status) of the core. the data bus exchange register (px) permits data to be passed between the 64-bit pm data bus and the 64-bit dm data bus, or between the 40-bit register file and the pm data bus. these reg- isters contain hardware to hand le the data width difference. timer a core timer that can generate pe riodic software interrupts. the core timer can be configured to use flag3 as a timer expired signal single-cycle fetch of instruction and four operands the adsp-21367/adsp-21368/adsp-21369 feature an enhanced harvard architecture in which the data memory (dm) bus transfers data and the program memory (pm) bus transfers both instructions and data (see figure 2 on page 4 ). with separate program and da ta memory buses and on-chip instruction cache, the processors can simultaneously fetch four operands (two over each data bus) and one instruction (from the cache), all in a single cycle. instruction cache the processors include an on-chip instruction cache that enables three-bus operation for fe tching an instruction and four data values. the cache is selectiveonly the instructions whose fetches conflict with pm bus data accesses are cached. this cache allows full-speed executio n of core, looped operations such as digital filter multiply -accumulates, and fft butterfly processing. data address generators with zero-overhead hardware circular buffer support the adsp-21367/adsp-21368/ad sp-21369 have two data address generators (dags). the dags are used for indirect addressing and implementing circular data buffers in hardware. circular buffers allo w efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and fourier transforms. the two dags contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 second- ary). the dags automatically handle address pointer wraparound, reduce overhead, increase performance, and sim- plify implementation. circular buffers can start and end at any memory location. flexible instruction set the 48-bit instruction word acco mmodates a variety of parallel operations for concise prog ramming. for example, the adsp-21367/adsp-21368/adsp-21369 can conditionally exe- cute a multiply, an add, and a subtract in both processing elements while branchin g and fetching up to four 32-bit values from memoryall in a single instruction. on-chip memory the processors contain two mega bits of internal ram and six megabits of internal mask-programmable rom. each block can be configured for different combin ations of code and data stor- age (see table 3 on page 6 ). each memory block supports single-cycle, independent accesses by the core processor and i/o
rev. e | page 6 of 60 | july 2009 adsp-21367/adsp-21368/adsp-21369 processor. the memory architecture, in combination with its separate on-chip buses, allows tw o data transfers from the core and one from the i/o processor, in a single cycle. the sram can be configured as a maximum of 64k words of 32-bit data, 128k words of 16- bit data, 42k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to two megabits. all of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. a 16-bit floating-point storage format is supported that effectively doubles the amount of data that can be stored on-chip. conversion between the 32-bit floating-point and 16-bit floating-point formats is per- formed in a single instruction. while each memory block can store combinations of code and data, accesses are most efficient when one block stores data usin g the dm bus for transfers, and the other block stores instructions and data using the pm bus for transfers. using the dm bus and pm buses, with one bus dedicated to each memory block, assures si ngle-cycle execution with two data transfers. in this case, the instruction must be available in the cache. on-chip memory bandwidth the internal memory architecture allows programs to have four accesses at the same time to any of the four blocks (assuming there are no block conflicts). th e total bandwidth is realized using the dmd and pmd buses (2 x64-bits, core clk) and the iod0/1 buses (2x32-bit, pclk). rom-based security the adsp-21367/adsp-21368/adsp-21369 have a rom secu- rity feature that provides hard ware support for securing user software code by preventing unauthorized reading from the internal code when enabled. wh en using this feature, the pro- cessor does not boot-load any external code, executing exclusively from internal rom. additionally, the processor is not freely accessible via the jtag port. instead, a unique 64-bit key, which must be scanned in through the jtag or test access port will be assigned to each cu stomer. the device will ignore a wrong key. emulation features and external boot modes are only available after the correct key is scanned. table 3. internal memory space 1 iop registers 0x0000 0000C0x0003 ffff long word (64 bits) extended precision normal or instruction word (48 bits) normal word (32 bits) short word (16 bits) block 0 rom (reserved) 0x0004 0000C0x0004 bfff block 0 rom (reserved) 0x0008 0000C0x0008 ffff block 0 rom (reserved) 0x0008 0000C0x0009 7fff block 0 rom (reserved) 0x0010 0000C0x0012 ffff reserved 0x0004 f000C0x0004 ffff reserved 0x0009 4000C0x0009 ffff reserved 0x0009 e000C0x0009 ffff reserved 0x0013 c000C0x0013 ffff block 0 sram 0x0004 c000C0x0004 efff block 0 sram 0x0009 0000C0x0009 3fff block 0 sram 0x0009 8000C0x0009 dfff block 0 sram 0x0013 0000C0x0013 bfff block 1 rom (reserved) 0x0005 0000C0x0005 bfff block 1 rom (reserved) 0x000a 0000C0x000a ffff block 1 rom (reserved) 0x000a 0000C0x000b 7fff block 1 rom (reserved) 0x0014 0000C0x0016 ffff reserved 0x0005 f000C0x0005 ffff reserved 0x000b 4000C0x000b ffff reserved 0x000b e000C0x000b ffff reserved 0x0017 c000C0x0017 ffff block 1 sram 0x0005 c000C0x0005 efff block 1 sram 0x000b 0000C0x000b 3fff block 1 sram 0x000b 8000C0x000b dfff block 1 sram 0x0017 0000C0x0017 bfff block 2 sram 0x0006 0000C0x0006 0fff block 2 sram 0x000c 0000C0x000c 1554 block 2 sram 0x000c 0000C0x000c 1fff block 2 sram 0x0018 0000C0x0018 3fff reserved 0x0006 1000C 0x0006 ffff reserved 0x000c 1555C0x000c 3fff reserved 0x000c 2000C0x000d ffff reserved 0x0018 4000C0x001b ffff block 3 sram 0x0007 0000C0x0007 0fff block 3 sram 0x000e 0000C0x000e 1554 block 3 sram 0x000e 0000C0x000e 1fff block 3 sram 0x001c 0000C0x001c 3fff reserved 0x0007 1000C0x0007 ffff reserved 0x000e 1555C0x000f ffff reserved 0x000e 2000C0x000f ffff reserved 0x001c 4000C0x001f ffff 1 the adsp-21368 and adsp-21369 processors include a customer-def inable rom block. please contact your analog devices sales repre sentative for additional details.
adsp-21367/adsp-21368/adsp-21369 rev. e | page 7 of 60 | july 2009 family peripheral architecture the adsp-21367/adsp-21368/adsp- 21369 family contains a rich set of peripherals that suppor t a wide variety of applications including high quality audio, medical imaging, communica- tions, military, test equipment, 3d graphics, speech recognition, motor control, imaging, and other applications. external port the external port interface supports access to the external mem- ory through core and dma acce sses. the external memory address space is divided into four banks. any bank can be pro- grammed as either asynchronous or synchronous memory. the external ports of the adsp-21367/ 8/9 processors are comprised of the following modules. ? an asynchronous memory in terface which communicates with sram, flash, and other devices that meet the stan- dard asynchronous sram access protocol. the ami supports 14m words of extern al memory in bank 0 and 16m words of external memory in bank 1, bank 2, and bank 3. ? an sdram controller that supports a glueless interface with any of the standard sdrams. the sdc supports 62m words of external memory in bank 0, and 64m words of external memory in bank 1, bank 2, and bank 3. ? arbitration logic to coordi nate core and dma transfers between internal and external memory over the external port. ? a shared memory interface th at allows the connection of up to four adsp-21368 processors to create shared exter- nal bus systems (adsp-21368 only). sdram controller the sdram controller provides an interface of up to four sepa- rate banks of industry-standard sdram devices or dimms, at speeds up to f sclk . fully compliant with the sdram standard, each bank has its own me mory select line (ms0 Cms3 ), and can be configured to contain betw een 16m bytes and 128m bytes of memory. sdram external memory address space is shown in table 4 . a set of programmable timing para meters is available to config- ure the sdram banks to support slower memory devices. the memory banks can be configured as either 32 bits wide for max- imum performance and bandwidth or 16 bits wide for minimum device count and lower system cost. the sdram controller address, data, clock, and control pins can drive loads up to distributed 30 pf loads. for larger memory systems, the sdram controller ex ternal buffer timing should be selected and external buffering should be provided so that the load on the sdram controller pins does not exceed 30 pf. external memory the external port provides a hi gh performance, glueless inter- face to a wide variety of industry-standard memory devices. the 32-bit wide bus can be used to interface to synchronous and/or asynchronous memory devices th rough the use of its separate internal memory controllers. th e first is an sdram controller for connection of industry-standard synchronous dram devices and dimms (dual inline memory module), while the second is an asynchronous me mory controller intended to interface to a variety of memory devices. four memory select pins enable up to four separate devices to coexist, supporting any desired combination of synchronous and asynchronous device types. non-sdram external memory address space is shown in table 5 . shared external memory the adsp-21368 processor suppor ts connecting to common shared external memory with other adsp-21368 processors to create shared external bus pr ocessor systems. this support includes: ? distributed, on-chip arbitratio n for the shared external bus ? fixed and rotating pr iority bus arbitration ? bus time-out logic ? bus lock multiple processors can share th e external bus with no addi- tional arbitration logic. arbitrat ion logic is included on-chip to allow the connection of up to four processors. bus arbitration is accomp lished through the br1C4 signals and the priority scheme for bus arbitr ation is determined by the set- ting of the rpba pin. table 8 on page 13 provides descriptions of the pins used in multiprocessor systems. external port throughput the throughput for the external port, based on 166 mhz clock and 32-bit data bus, is 221m bytes/s for the ami and 664m bytes/s for sdram. table 4. external memory for sdram addresses bank size in words address range bank 0 62m 0x0020 0000C0x03ff ffff bank 1 64m 0x0400 0000C0x07ff ffff bank 2 64m 0x0800 0000C0x0bff ffff bank 3 64m 0x0c00 0000C0x0fff ffff table 5. external memory for non-sdram addresses bank size in words address range bank 0 14m 0x0020 0000C0x00ff ffff bank 1 16m 0x0400 0000C0x04ff ffff bank 2 16m 0x0800 0000C0x08ff ffff bank 3 16m 0x0c00 0000C0x0cff ffff
rev. e | page 8 of 60 | july 2009 adsp-21367/adsp-21368/adsp-21369 asynchronous memory controller the asynchronous memory contro ller provides a configurable interface for up to four sepa rate banks of memory or i/o devices. each bank can be independently programmed with dif- ferent timing paramete rs, enabling connection to a wide variety of memory devices including sram, rom, flash, and eprom, as well as i/o devices that in terface with standard memory control lines. bank 0 occupies a 14m word window and banks 1, 2, and 3 occupy a 16m word wind ow in the processors address space but, if not fully populated, these windows are not made contiguous by the memory contro ller logic. the banks can also be configured as 8-bit, 16-bit, or 32-bit wide buses for ease of interfacing to a range of memo ries and i/o devices tailored either to high performance or to low cost and power. pulse-width modulation the pwm module is a flexible , programmable, pwm waveform generator that can be programme d to generate the required switching patterns for various a pplications related to motor and engine control or audio power control. the pwm generator can generate either center-aligned or edge-aligned pwm wave- forms. in addition, it can generate complementary signals on two outputs in paired mode or independent signals in non- paired mode (applicable to a single group of four pwm waveforms). the entire pwm module has four groups of four pwm outputs each. therefore, this module generates 16 pwm outputs in total. each pwm group produces two pairs of pwm signals on the four pwm outputs. the pwm generator is capable of operating in two distinct modes while generating center-aligned pwm waveforms: single update mode or double update mode. in single update mode, the duty cycle values are prog rammable only once per pwm period. this results in pwm pa tterns that are symmetrical about the midpoint of the pw m period. in double update mode, a second updating of th e pwm registers is implemented at the midpoint of the pwm period. in this mode, it is possible to produce asymmetrical pwm patterns that produce lower harmonic distortion in 2-phase pwm inverters. digital applications interface (dai) the digital applications interface (dai ) provide the ability to connect various peripherals to any of the dsps dai pins (dai_p20C1). programs make th ese connections using the sig- nal routing unit (sru1), shown in figure 1 . the sru is amatrix routing unit (or group of multiplexers) that enable the peripherals provided by the dai to be intercon- nected under software control. this allows easy use of the associated peripherals for a much wider variety of applications by using a larger set of algorithms than is possible with noncon- figurable signal paths. the dai include eight serial port s, an s/pdif receiver/trans- mitter, four precision clock genera tors (pcg), eight channels of synchronous sample rate conver ters, and an input data port (idp). the idp provides an additional input path to the processor core, configurable as either eight channels of i 2 s serial data or as seven channels plus a single 20-bit wide synchronous parallel data acquisition port. each data channel has its own dma channel that is independen t from the processors serial ports. for complete information on using the dai, see the adsp-21368 sharc proces sor hardware reference . serial ports the processors feature eight sync hronous serial ports (sports) that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devi ces such as analog devices ad183x family of audio codecs , adcs, and dacs. the serial ports are made up of two data lines, a clock, and frame sync. the data lines can be programmed to either transmit or receive and each data line has a dedicated dma channel. serial ports are enabled via 16 programmable and simultaneous receive or transmit pins that support up to 32 transmit or 32 receive channels of audio data when all eight sports are enabled, or eight full duplex tdm streams of 128 channels per frame. the serial ports operate at a maximum data rate of 50 mbps. serial port data can be automatically transferred to and from on-chip memory via dedicated dma channels. each of the serial ports can work in conjunct ion with another serial port to provide tdm support. one sport provides two transmit sig- nals while the other sport provides the two receive signals. the frame sync and clock are shared. serial ports operate in five modes: ? standard dsp serial mode ? multichannel (tdm) mode with support for packed i 2 s mode ?i 2 s mode ?packed i 2 s mode ? left-justified sa mple pair mode left-justified sample pair mode is a mode where in each frame sync cycle two samples of data are transmitted/receivedone sample on the high segment of the frame sync, the other on the low segment of the frame sync. programs have control over var- ious attributes of this mode. each of the serial ports supports the left-justified sample pair and i 2 s protocols (i 2 s is an industry-standard interface com- monly used by audio codecs, adcs, and dacs such as the analog devices ad183x family), with two data pins, allowing four left-justified sample pair or i 2 s channels (using two stereo devices) per serial port, with a maximum of up to 32 i 2 s chan- nels. the serial ports permit little-endian or big-endian transmission formats an d word lengths selectable from 3 bits to 32 bits. for the left-justified sample pair and i 2 s modes, data- word lengths are selectable betw een 8 bits and 32 bits. serial ports offer selectable synchron ization and transmit modes as well as optional -law or a-law companding selection on a per channel basis. serial port cloc ks and frame syncs can be inter- nally or externally generated.
adsp-21367/adsp-21368/adsp-21369 rev. e | page 9 of 60 | july 2009 the serial ports also contain fr ame sync error detection logic where the serial ports detect fram e syncs that arrive early (for example, frame syncs that arrive while the transmission/recep- tion of the previous word is occurring). all the serial ports also share one dedicated error interrupt. s/pdif-compatible digital audio receiver/transmitter the s/pdif receiver/transmitter has no separate dma chan- nels. it receives audio data in serial format and converts it into a biphase encoded signal. the serial data input to the receiver/transmitter can be formatted as left-justified, i 2 s, or right-justified with word widt hs of 16, 18, 20, or 24 bits. the serial data, clock, and frame sync inputs to the s/pdif receiver/transmitter are routed th rough the signal routing unit (sru). they can come from a va riety of sources such as the sports, external pins, the precision clock generators (pcgs), or the sample rate converters (src) and are controlled by the sru control registers. synchronous/asynchronous sample rate converter the sample rate converter (src) contains four src blocks and is the same core as that us ed in the ad1896 192 khz stereo asynchronous sample rate conver ter and provides up to 128 db snr. the src block is used to perform synchronous or asyn- chronous sample rate conversi on across indepe ndent stereo channels, without using internal processor resources. the four src blocks can also be configur ed to operate to gether to con- vert multichannel audio data without phase mismatches. finally, the src can be used to clean up audio data from jittery clock sources such as the s/pdif receiver. input data port the idp provides up to eight se rial input channelseach with its own clock, frame sync, and data inputs. the eight channels are automatically multiplexed into a single 32-bit by eight-deep fifo. data is always formatted as a 64-bit frame and divided into two 32-bit words. the serial protocol is designed to receive audio channels in i2s, left-justified sample pair , or right-justi- fied mode. one frame sync cycle indicates one 64-bit left/right pair, but data is sent to the fifo as 32-bit words (that is, one- half of a frame at a time). the processor supports 24- and 32-bit i 2 s, 24- and 32-bit left-justified , and 24-, 20-, 18- and 16-bit right-justified formats. precision clock generators the precision clock generators (pcg) consist of four units, each of which generates a pair of signals (clock and frame sync) derived from a clock input signal. the units, a b, c, and d, are identical in functionality and operate independently of each other. the two signals generated by each unit are normally used as a serial bit clock/frame sync pair. digital peripheral interface (dpi) the digital peripheral interfac e provides connections to two serial peripheral interface port s (spi), two univ ersal asynchro- nous receiver-transmitters (uarts ), a 2-wire interface (twi), 12 flags, and three general-purpose timers. serial peripheral (compatible) interface the processors contain two serial peripheral interface ports (spis). the spi is an industry-s tandard synchronous serial link, enabling the spi-compatible port to communicate with other spi-compatible devices. the spi consists of two data pins, one device select pin, and one clock pin. it is a full-duplex synchronous serial interface, su pporting both master and slave modes. the spi port can operat e in a multimaster environment by interfacing with up to four other spi-compatible devices, either acting as a master or slave device. the adsp-21367/ adsp-21368/adsp-21369 spi-compat ible peripheral imple- mentation also features programmable baud rate and clock phase and polarities. the spi-comp atible port uses open-drain drivers to support a multimaste r configuration and to avoid data contention. uart port the processors provide a full-du plex universal asynchronous receiver/transmitter (uart) port , which is fully compatible with pc-standard uarts. the ua rt port provides a simpli- fied uart interface to other peripherals or hosts, supporting full-duplex, dma-supported, asynchronous transfers of serial data. the uart also has multiprocessor commun ication capa- bility using 9-bit address detection. this allows it to be used in multidrop networks through the rs-485 data interface standard. the uart port also incl udes support for five data bits to eight data bits, one stop bit or two stop bits, and none, even, or odd parity. the uart po rt supports two modes of operation: ? pio (programmed i/o) C the processor sends or receives data by writing or reading i/o-mapped uart registers. the data is double-buffered on both transmit and receive. ? dma (direct memory access) C the dma controller trans- fers both transmit and receive data. this reduces the number and frequency of interrupts required to transfer data to and from memory. the uart has two dedicated dma channels, one for transmit and one for receive. these dma channels have lower defa ult priority than most dma channels because of their re latively low service rates. the uart ports baud rate, seri al data format, error code gen- eration and status, and interrupts are programmable: ? supporting bit rates ranging from (f sclk /1,048,576) to (f sclk /16) bits per second. ? supporting data formats from 7 bits to 12 bits per frame. ? both transmit and receive operations can be configured to generate maskable interrupts to the processor. where the 16-bit uart_divisor comes from the dlh register (most significant eight bits) and dll register (least significant eight bits). in conjunction with the general- purpose timer functions, auto- baud detection is supported.
rev. e | page 10 of 60 | july 2009 adsp-21367/adsp-21368/adsp-21369 peripheral timers three general-purpose timers ca n generate periodic interrupts and be independently set to op erate in one of three modes: ? pulse waveform generation mode ? pulse width count/capture mode ? external event watchdog mode each general-purpose timer has one bidirectional pin and four registers that implement its mode of operation: a 6-bit configu- ration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulse width register . a single control and status register enables or disables all three general-purpose timers independently. 2-wire interface port (twi) the twi is a bidirectional 2-wire serial bus used to move 8-bit data while maintaining compliance with the i 2 c bus protocol. the twi master incorporates the following features: ? simultaneous master and sl ave operation on multiple device systems with suppo rt for multimaster data arbitration ? digital filtering and timed event processing ? 7-bit and 10-bit addressing ? 100 kbps and 400 kbps data rates ? low interrupt rate i/o processor features the i/o processor prov ides many channels of dma, and con- trols the extensive set of peripherals described in the previous sections. dma controller the processors on-chip dma controller allows data transfers without processor intervention . the dma controller operates independently and invisibly to the processor core, allowing dma operations to occur while th e core is simultaneously exe- cuting its program instructio ns. dma transfers can occur between the processors internal me mory and its serial ports, the spi-compatible (serial peripher al interface) ports, the idp (input data port), the parallel da ta acquisition port (pdap), or the uart. thirty four channels of dma are available on the adsp-2136x processors as shown in table 6 . delay line dma the adsp-21367/adsp-21368/adsp-21369 processors pro- vide delay line dma functionalit y. this allows processor reads and writes to external delay line buffers (in external memory, sram, or sdram) with limited core interaction. system design the following sections provide an introduction to system design options and power supply issues. program booting the internal memory of the processors can be booted up at sys- tem power-up from an 8-bit eprom via the external port, an spi master or slave, or an internal boot. booting is determined by the boot configuratio n (boot_cfg1C0) pins (see table 7 and the processor hardware refe rence). selection of the boot source is controlled via the spi as either a master or slave device, or it can immediately begin executing from rom. power supplies the processors have separate power supply connections for the internal (v ddint ), external (v ddext ), and analog (a vdd /a vss ) power supplies. the internal and analog supplies must meet the 1.3 v requirement for the 400 mhz device and 1.2 v for the 333 mhz and 266 mhz devices. the external supply must meet the 3.3 v requirement. all external supply pins must be con- nected to the sa me power supply. note that the analog supply pin (a vdd ) powers the processors internal clock generator pll. to produce a stable clock, it is rec- ommended that pcb designs use an external filter circuit for the a vdd pin. place the filter components as close as possible to the a vdd /a vss pins. for an example circuit, see figure 3 . (a recom- mended ferrite chip is the murata blm18ag102sn1d). to reduce noise coupling, the pcb should use a parallel pair of power and ground planes for v ddint and gnd. use wide traces to connect the bypass capacitors to the analog power (a vdd ) and ground (a vss ) pins. note that the a vdd and a vss pins specified in figure 3 are inputs to the processo r and not the analog ground plane on the boardthe a vss pin should connect directly to dig- ital ground (gnd) at the chip. table 6. dma channels peripheral dma channels sports 16 pdap 8 spi 2 uart 4 external port 2 memory-to-memory 2 table 7. boot mode selection boot_cfg1C0 booting mode 00 spi slave boot 01 spi master boot 10 eprom/flash boot 11 reserved
adsp-21367/adsp-21368/adsp-21369 rev. e | page 11 of 60 | july 2009 target board jtag emulator connector analog devices dsp tools product line of jtag emulators uses the ieee 1149.1 jtag test ac cess port of the adsp-21367/ adsp-21368/adsp-21369 processo rs to monitor and control the target board processor duri ng emulation. analog devices dsp tools product line of jtag emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, an d processor stacks. the processors jtag interface ensures that the emulator will not a ffect target system loading or timing. for complete information on analog devices sharc dsp tools product line of jtag emulator operation, see the appro- priate emulator hardware users guide. development tools the processors are supported wi th a complete set of cross- core ? software and hardware de velopment tools, including analog devices emulators and visualdsp++ ? development environment. the same emulator hardware that supports other sharc processors also fully emulates the adsp-21367/ adsp-21368/adsp-21369. the visualdsp++ project management environment lets pro- grammers develop and debug an application. this environment includes an easy to use assembler (which is based on an alge- braic syntax), an archiver (librarian/library builder), a linker, a loader, a cycle-accura te instruction-level simulator, a c/c++ compiler, and a c/c++ runtime library that includes dsp and mathematical functions. a key point for these tools is c/c++ code efficiency. the compiler ha s been developed for efficient translation of c/c++ code to dsp assembly. the sharc has architectural features that improve the efficiency of compiled c/c++ code. the visualdsp++ debugger has a number of important fea- tures. data visualization is enhanced by a plotting package that offers a significant level of flexibility. this graphical representa- tion of user data enables the programmer to quickly determine the performance of an algorithm. as algorithms grow in com- plexity, this capability can have increasing significance on the designers development schedule, increasing productivity. sta- tistical profiling enables the pr ogrammer to nonintrusively poll the processor as it is running the program. this feature, unique to visualdsp++, enables the software developer to passively gather important code executio n metrics without interrupting the real-time characteristics of the program. essentially, the developer can identify bottleneck s in software quickly and effi- ciently. by using the profiler , the programmer can focus on those areas in the program that impact performance and take corrective action. debugging both c/c++ and assembly programs with the visualdsp++ debugger, programmers can: ? view mixed c/c++ and assembly code (interleaved source and object information) ? insert breakpoints ? set conditional breakpoints on registers, memory, and stacks ? perform linear or statistical profiling of program execution ? fill, dump, and graphically plot the contents of memory ? perform source level debugging ? create custom debugger windows the visualdsp++ idde lets programmers define and manage dsp software development. its di alog boxes and property pages let programmers configure and manage all of the sharc devel- opment tools, including the colo r syntax highlighting in the visualdsp++ editor. this capability permits programmers to: ? control how the development tools process inputs and generate outputs ? maintain a one-to-one correspondence with the tools command line switches the visualdsp++ kernel (vdk) incorporates scheduling and resource management tailored sp ecifically to address the mem- ory and timing constraints of dsp programming. these capabilities enable engineers to develop code more effectively, eliminating the need to start from the very beginning, when developing new application code. the vdk features include threads, critical and unschedule d regions, semaphores, events, and device flags. the vdk also supports priority-based, pre- emptive, cooperative, and time-s liced scheduling approaches. in addition, the vdk was designed to be scalable. if the application does not use a specific feature, the support code for that feature is excluded from the target system. because the vdk is a library, a developer can decide whether to use it or not. the vdk is integrated into the visualdsp++ development environment, but can also be used via standard command line tools. when the vdk is used, the development environment assists th e developer with many error-prone tasks and assists in managi ng system resources, automating the gen- eration of various vdk-based objects, and vi sualizing the system state, when debugging an application that uses the vdk. use the expert linker to visually manipulate the placement of code and data on the embedded system. view memory utiliza- tion in a color-coded graphical form, easily move code and data to different areas of the processor or external memory with a drag of the mouse and examine runtime stack and heap usage. the expert linker is fully compatible with the existing linker def- inition file (ldf), allowing th e developer to move between the graphical and textual environments. figure 3. analog power (a vdd ) filter circuit hi- ferrite bead chip locate all component s s ss s ss s 3
rev. e | page 12 of 60 | july 2009 adsp-21367/adsp-21368/adsp-21369 in addition to the software and hardware development tools available from analog devices, third parties provide a wide range of tools supporting the sharc processor family. hard- ware tools include sharc processor pc plug-in cards. third- party software tools include dsp libraries, real-time operating systems, and block diagram design tools. designing an emulator-compatible dsp board (target) the analog devices family of emulators are tools that every dsp developer needs to test an d debug hardware and software systems. analog devices has supp lied an ieee 1149.1 jtag test access port (tap) on each jtag dsp. nonintrusive in-circuit emulation is assured by the use of the processors jtag inter- facethe emulator does not affe ct target syst em loading or timing. the emulator uses the tap to access the internal fea- tures of the processor, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. the processor must be halted to send data and com- mands, but once an operatio n has been completed by the emulator, the dsp system is set running at full speed with no impact on system timing. to use these emulators, the targ et board must include a header that connects the dsps jtag port to the emulator. for details on target board desi gn issues including mechanical layout, single processor connections, signal buffering, signal ter- mination, and emulator pod logic, see the ee-68: analog devices jtag emulation technical reference on the analog devices website ( www.analog.com )use site search on ee-68. this document is updated regularly to keep pace with improvements to emulator support. evaluation kit analog devices offers a range of ez-kit lite ? evaluation plat- forms to use as a cost-effective method to learn more about developing or prototyping appl ications with analog devices processors, platforms, and softwa re tools. each ez-kit lite includes an evaluation board along with an evaluation suite of the visualdsp++ development and debugging environment with the c/c++ compiler, assemble r, and linker. also included are sample applicat ion programs, power supply, and a usb cable. all evaluation versions of the software tools are limited for use only with the ez-kit lite product. the usb controller on the ez-kit lite board connects the board to the usb port of the users pc, enabling the visualdsp++ evaluation suite to emulate the on-board proces- sor in-circuit. this permits the customer to download, execute, and debug programs for the ez-kit lite system. it also allows in-circuit programming of the on -board flash device to store user-specific boot co de, enabling the board to run as a stand- alone unit without being connected to the pc. with a full version of visualdsp ++ installed (sold separately), engineers can develop software for the ez-kit lite or any custom-defined system. connecting one of analog devices jtag emulators to the ez-kit li te board enables high speed, nonintrusive emulation. additional information this data sheet provides a general overview of the adsp-21367/adsp-21368/adsp-21369 architecture and func- tionality. for detailed inform ation on the adsp-2136x family core architecture and inst ruction set, refer to the adsp-21368 sharc processor hardware reference and the sharc processor programming reference .
adsp-21367/adsp-21368/adsp-21369 rev. e | page 13 of 60 | july 2009 pin function descriptions the following symbols appear in the type column of table 8 : a = asynchronous, g = ground, i = input, o = output, o/t = output three-state, p = power supply, s = synchronous, (a/d) = active drive, (o/d) = open-drain, (pd) = pull-down resistor, (pu) = pull-up resistor. the adsp-21367/adsp-21368/adsp-21369 sharc proces- sors use extensive pin multiplexing to achieve a lower pin count. for complete information on th e multiplexing scheme, see the adsp-21368 sharc proces sor hardware reference , system design chapter. table 8. pin descriptions name type state during/ after reset (id = 00x) description addr 23C0 o/t (pu) 1 pulled high/ driven low external address. the processors output addresses for external memory and peripher- als on these pins. data 31C0 i/o (pu) 1 pulled high/ pulled high external data. data pins can be multiplexed to support external memory interface data (i/o), the pdap (i), flags (i/o), and pwm (o). after reset, all data pins are in emif mode and flag(0-3) pins are in flags mode (default). when configured using the idp_pdap_ctl register, idp channel 0 scans the external port data pins for parallel input data. ack i (pu) 1 memory acknowledge. external devices can deassert ack (low) to add wait states to an external memory access. ack is used by i/o devices, memory contro llers, or other periph- erals to hold off completion of an external memory access. ms 0C1 o/t (pu) 1 pulled high/ driven high memory select lines 0C1. these lines are asserted (low) as chip selects for the corre- sponding banks of external memory. the ms 3-0 lines are decoded memory address lines that change at the same time as the other address lines. when no external memor y access is occurring, the ms 3-0 lines are inactive; they are active, however, when a conditional memory access instruction is executed, whether or not the condition is true. the ms 1 pin can be used in eport/flash boot mode. see the processor hardware reference for more information. rd o/t (pu) 1 pulled high/ driven high external port read enable. rd is asserted whenever the processors read a word from external memory. wr o/t (pu) 1 pulled high/ driven high external port write enable. wr is asserted when the processors write a word to external memory. flag[0]/irq0 i/o flag[0] input flag0/interrupt request 0. flag[1]/irq1 i/o flag[1] input flag1/interrupt request 1. flag[2]/irq2 / ms 2 i/o with pro- grammable pu (for ms mode) flag[2] input flag2/interrupt request 2/memory select 2. flag[3]/ tmrexp/ms 3 i/o with pro- grammable pu (for ms mode) flag[3] input flag3/timer expired/memory select 3.
rev. e | page 14 of 60 | july 2009 adsp-21367/adsp-21368/adsp-21369 sdras o/t (pu) 1 pulled high/ driven high sdram row address strobe. connect to sdrams ras pin. in conjunction with other sdram command pins, defines the oper ation for the sdram to perform. sdcas o/t (pu) 1 pulled high/ driven high sdram column address select. connect to sdrams cas pin. in conjunction with other sdram command pins, defines the oper ation for the sdram to perform. sdwe o/t (pu) 1 pulled high/ driven high sdram write enable. connect to sdrams we or w buffer pin. sdcke o/t (pu) 1 pulled high/ driven high sdram clock enable. connect to sdrams cke pin. enables and disables the clk signal. for details, see the data sheet supplied with the sdram device. sda10 o/t (pu) 1 pulled high/ driven low sdram a10 pin. enables applications to refresh an sdram in parallel with non- sdram accesses. this pin replaces the dsps a10 pin only during sdram accesses. sdclk0 o/t high-z/driving sdram clock output 0. clock driver for this pin differs from all other clock drivers. see figure 39 on page 48 . sdclk1 o/t sdram clock output 1. additional clock for sdram devices. for systems with multiple sdram devices, handles the increased clock lo ad requirements, elim inating need of off- chip clock buffers. either sdclk1 or both sd clkx pins can be three-stated. clock driver for this pin differs from all other clock drivers. see figure 39 on page 48 . the sdclk1 signal is only available on the sbga package. sdclk1 is not available on the lqfp_ep package. dai _p 20C1 i/o with pro- grammable pu 2 pulled high/ pulled high digital applications interface . these pins provide the physical interface to the dai sru. the dai sru configuration registers define the combination of on-chip audiocentric peripheral inputs or outputs connected to th e pin, and to the pins output enable. the configuration registers then determines the exact behavior of th e pin. any input or output signal present in the dai sru may be routed to any of these pins. the dai sru provides the connection from the serial port s (8), the src module , the s/pdif module, input data ports (2), and the precision clock generators (4), to the dai_p20C1 pins. pull- ups can be disabled via the dai_pin_pullup register. dpi _p 14C1 i/o with pro- grammable pu 2 pulled high/ pulled high digital peripheral interface. these pins provide the physic al interface to the dpi sru. the dpi sru configuration registers define the combination of on-chip peripheral inputs or outputs connected to the pin and to th e pins output enable. the configuration registers of these peripherals then determines the exact behavior of the pin. any input or output signal present in the dpi sru may be routed to any of these pins. the dpi sru provides the connection from the timers (3), spis (2), uarts (2), flags (12) twi (1), and general-purpose i/o (9) to the dpi_p14C1 pins . the twi output is an open-drain output so the pins used for i 2 c data and clock should be connected to logic level 0. pull-ups can be disabled via the dpi_pin_pullup register. tdi i (pu) test data input (jtag). provides serial data for the boundary scan logic. tdo o/t test data output (jtag). serial scan output of the boundary scan path. tms i (pu) test mode select (jtag). used to control the test state machine. tck i test clock (jtag). provides a clock for jtag boundary scan. tck must be asserted (pulsed low) after power-up, or held low for proper operation of the processor trst i (pu) test reset (jtag). resets the test state machine. trst must be asserted (pulsed low) after power-up or held low for proper operation of the processor. table 8. pin descriptions (continued) name type state during/ after reset (id = 00x) description
adsp-21367/adsp-21368/adsp-21369 rev. e | page 15 of 60 | july 2009 emu o/t (pu) emulation status. must be connected to the adsp-21367/adsp-21368/ adsp-21369 analog devices dsp tools product line of jtag emulator target board con- nectors only. clk_cfg 1C0 i core/clkin ratio control. these pins set the start-up clock frequency. see the processor hardware reference for a description of the clock configuration modes. note that the operating frequency can be changed by programming the pll multiplier and divider in the pmctl register at any time after the core comes out of reset. clkin i local clock in. used with xtal. clkin is the processors clock input. it configures the processors to use either its internal clock ge nerator or an external clock source. connect- ing the necessary components to clkin and xt al enables the internal clock generator. connecting the external clock to clkin while leaving xtal unconnected configures the processor to use an external clock such as an external clock oscillator. clkin may not be halted, changed, or operated below the specified frequency. xtal o crystal oscillator terminal. used in conjunction with clkin to drive an external crystal. reset i processor reset. resets the processor to a known stat e. upon deassertion, there is a 4096 clkin cycle latency for the pll to lock. after this time, the core begins program execution from the hardware reset vector address. the reset input must be asserted (low) at power- up. resetout od r i v e n l o w / driven high reset out. drives out the core reset signal to an external device. boot_cfg 1C0 i boot configuration select. these pins select the boot mode for the processor. the boot_cfg pins must be valid before rese t is asserted. see the processor hardware reference for a description of the boot modes. br 4C1 i/o (pu) 1 pulled high/ pulled high external bus request. used by the adsp-21368 processor to arbitrate for bus master- ship. a processor only drives its own br x line (corresponding to the value of its id2-0 inputs) and monitors all others. in a system wi th less than four processors, the unused br x pins should be tied high; the processors own br x line must not be tied high or low because it is an output. id 2C0 i (pd) processor id. determines which bus request (br 4C1 ) is used by the adsp-21368 processor. id = 001 corresponds to br 1, id = 010 corresponds to br 2 , and so on. use id = 000 or 001 in single-processor systems. these lines are a system configuration selection that should be hardwired or only changed at reset. id = 101,110, and 111 are reserved. rpba i (pu) 1 rotating priority bus arbitration select. when rpba is high, rotating priority for the adsp-21368 external bus arbitration is selected. when rpba is low, fixed priority is selected. this signal is a system configurat ion selection which must be set to the same value on every processor in the system. 1 the pull-up is always enabled on the adsp-21367 and adsp-21369 pr ocessors. the pull-up on the adsp-21368 processor is only enab led on the processor with id 2C0 = 00x 2 pull-up can be enabled/disabled, value of pull-up cannot be programmed. table 8. pin descriptions (continued) name type state during/ after reset (id = 00x) description
rev. e | page 16 of 60 | july 2009 adsp-21367/adsp-21368/adsp-21369 specifications operating conditions parameter 1 1 specifications subject to change without notice. description 400 mhz 366 mhz 350 mhz 333 mhz 266 mhz min max min max min max unit v ddint internal (core) supply voltage 1.25 1.35 1.235 1.365 1.14 1.26 v a vdd analog (pll) supply voltage 1.25 1.35 1.235 1.365 1.14 1.26 v v ddext external (i/o) supply voltage 3.13 3.47 3.13 3.47 3.13 3.47 v v ih 2 2 applies to input and bidirectional pins: datax, ack, rpba, brx , idx, flagx, dai_px, dpi_px, boot_cfgx, clk_cfgx, reset , tck, tms, tdi, trst . high level input voltage @ v ddext = max 2.0 v ddext + 0.5 2.0 v ddext + 0.5 2.0 v ddext + 0.5 v v il 2 low level input voltage @ v ddext = min C0.5 +0.8 C0.5 +0.8 C0.5 +0.8 v v ih _ clkin 3 3 applies to input pin clkin. high level input voltage @ v ddext = max 1.74 v ddext + 0.5 1.74 v ddext + 0.5 1.74 v ddext + 0.5 v v il _ clkin 3 low level input voltage @ v ddext = min C0.5 +1.1 C0.5 +1.1 C0.5 +1.1 v t j junction temperature 208-lead lqfp_ep @ t ambient 0 c to 70 c n/a n/a 0 110 0 110 c t j junction temperature 208-lead lqfp_ep @ t ambient C40 c to +85 c n/a n/a n/a n/a C40 +120 c t j junction temperature 256-ball bga_ed @ t ambient 0 c to 70 c 0 95 n/a n/a 0 105 c t j junction temperature 256-ball bga_ed @ t ambient C40 c to +85 c n/a n/a n/a n/a 0 105 c
adsp-21367/adsp-21368/adsp-21369 rev. e | page 17 of 60 | july 2009 electrical characteristics parameter description test conditions min typ max unit v oh 1 high level output voltage @ v ddext = min, i oh = C1.0 ma 2 2.4 v v ol 1 low level output voltage @ v ddext = min, i ol = 1.0 ma 2 0.4 v i ih 3, 4 high level input current @ v ddext = max, v in = v ddext max 10 a i il 3, 5, 6 low level input current @ v ddext = max, v in = 0 v 10 a i ihpd 5 high level input current pull-down @ v ddext = max, v in = 0 v 250 a i ilpu 4 low level input current pull-up @ v ddext = max, v in = 0 v 200 a i ozh 7, 8 three-state leakage current @ v ddext = max, v in = v ddext max 10 a i ozl 7, 9 three-state leakage current @ v ddext = max, v in = 0 v 10 a i ozlpu 8 three-state leakage current pull-up @ v ddext = max, v in = 0 v 200 a i dd - intyp 10 supply current (internal) t cclk = 3.75 ns, v ddint = 1.2 v, 25c t cclk = 3.00 ns, v ddint = 1.2 v, 25c t cclk = 2.85 ns, v ddint = 1.3 v, 25c t cclk = 2.73 ns, v ddint = 1.3 v, 25c t cclk = 2.50 ns, v ddint = 1.3 v, 25c 700 900 1050 1080 1100 ma ma ma ma ma ai dd 11 supply current (analog) a vdd = max 11 ma c in 12, 13 input capacitance f in = 1 mhz, t case = 25c, v in = 1.3 v 4.7 pf 1 applies to output and bidirecti onal pins: addrx, datax, rd , wr , msx , brx , flagx, dai_px, dpi_px, sdras , sdcas , sdwe , sdcke, sda10, sdclkx, emu , tdo. 2 see output drive currents on page 48 for typical drive current capabilities. 3 applies to input pins without internal pull- ups: boot_cfgx, clk_cfgx, clkin, reset , tck. 4 applies to input pins with internal pull-ups: ack, rpba, tms, tdi, trst . 5 applies to input pins with internal pull-downs: idx. 6 applies to input pins with interna l pull-ups disabled: ack, rpba. 7 applies to three-statable pins without internal pull-ups: flagx, sdclkx, tdo. 8 applies to three-statable pins with internal pull-ups: addrx, datax, rd , wr , msx , brx , dai_px, dpi_px, sdras , sdcas, sdwe , sdcke, sda10, emu . 9 applies to three-statable pins with internal pull-ups disabled: addrx, datax, rd , wr , msx , brx , dai_px, dpi_px, sdras , sdcas , sdwe , sdcke, sda10 10 see estimating power dissipation for adsp-21368 sharc pr ocessors (ee-299) for further information. 11 characterized, but not tested. 12 applies to all signal pins. 13 guaranteed, but not tested.
rev. e | page 18 of 60 | july 2009 adsp-21367/adsp-21368/adsp-21369 package information the information presented in figure 4 provides details about the package branding fo r the adsp-21367/adsp-21368/ adsp-21369 processors. for a comp lete listing of product avail- ability, see ordering guide on page 58 . esd caution maximum power dissipation see estimating power dissipation for adsp-21368 sharc pro- cessors (ee-299) for detailed ther mal and power information regarding maximum power dissi pation. for information on package thermal specifications, see thermal characteristics on page 50 . absolute maximum ratings stresses greater than those listed in table 10 may cause perma- nent damage to the device. these are stress ratings only; functional operation of the device at these or any other condi- tions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. timing specifications use the exact timing information given. do not attempt to derive parameters from the addition or subtraction of others. while addition or subtraction would yield meaningful results for an individual device, the va lues given in this data sheet reflect statistical variations and worst cases. consequently, it is not meaningful to add parameters to derive longer times. see figure 40 on page 48 under test conditions for voltage refer- ence levels. switching characteristics specify how the processor changes its signals. circuitry external to the processor must be designed for compatibility with these signal characteristics. switching char- acteristics describe what the processor will do in a given circumstance. use switching charac teristics to en sure that any timing requirement of a device connected to the processor (such as memory) is satisfied. timing requirements apply to signals that are controlled by cir- cuitry external to the processor, such as the data input for a read operation. timing requirements guarantee that the processor operates correctly with other devices. core clock requirements the processors internal clock (a multiple of clkin) provides the clock signal for timing inte rnal memory, processor core, and serial ports. during reset, prog ram the ratio between the proces- sors internal clock frequency and external (clkin) clock frequency with the clk_cfg1C0 pins. the processors internal clock sw itches at higher frequencies than the system input clock (clk in). to generate the internal clock, the processor uses an in ternal phase-locked loop (pll, see figure 5 ). this pll-based clocki ng minimizes the skew between the system clock (clkin ) signal and the processors internal clock. voltage controlled oscillator in application designs, the pll multiplier value should be selected in such a way that the vco frequency never exceeds f vco specified in table 13 . ? the product of clkin and pllm must never exceed 1/2 of f vco (max) in table 13 if the input divider is not enabled (indiv = 0). figure 4. typical package brand table 9. package brand information brand key field description t temperature range pp package type z rohs compliant option cc see ordering guide vvvvvv.x assembly lot code n.n silicon revision # rohs compliant designation yyww date code vvvvvv.x n.n tppz-cc s ads p-21 3 6x a #yyww country_of_ori g in esd (electrostatic discharge) sensitive device. charged devices and circuit boards can discharge without detection. although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy esd. therefore, proper esd precautions should be taken to avoid performance degradation or loss of functionality. table . absolute aimum atings parameter rating internal (core) supply voltage (v ddint )C0.3 v to +1.5 v analog (pll) supply voltage (a vdd )C0.3 v to +1.5 v external (i/o) supply voltage (v ddext )C0.3 v to +4.6 v input voltage C0.5 v to +3.8 v output voltage swing C0.5 v to v ddext + 0.5 v load capacitance 200 pf storage temperature range C65 c to +150 c junction temperature under bias 125 c
adsp-21367/adsp-21368/adsp-21369 rev. e | page 19 of 60 | july 2009 ? the product of clkin and pllm must never exceed f vco (max) in table 13 if the input divider is enabled (indiv = 1). the vco frequency is calculated as follows: f vco = 2 pllm f input f cclk = (2 pllm f input ) (2 plld ) where: f vco = vco output pllm = multiplier value programm ed in the pmctl register. during reset, the pllm value is derived from the ratio selected using the clk_cfg pins in hardware. plld = divider value 1, 2, 4, or 8 based on the plld value pro- grammed on the pmctl register. during reset this value is 1. f input = input frequency to the pll. f input = clkin when the input divider is disabled or f input = clkin 2 when the input divider is enabled note the definitions of the clock periods that are a function of clkin and the appropriate ra tio control shown in and table 11 . all of the timing specifications for the adsp-2136x peripherals are define d in relation to t pclk . see the peripheral spe- cific timing section for each peripherals timing information. figure 5 shows core to clkin relati onships with external oscil- lator or crystal. the shaded di vider/multiplier blocks denote where clock ratios can be set through hardware or software using the power management control register (pmctl). for more information, see the pr ocessor hardware reference. table 11. clock periods timing requirements description t ck clkin clock period t cclk processor core clock period t pclk peripheral clock period = 2 t cclk figure 5. core clock and system clock relationship to clkin loop filter clkin pclk s dclk s dram divider pmctl (pllbp) b p a s s m u x divide b 2 pmctl ( s dckr) cclk b p a s s m u x pll xtal clkin divider pll multiplier buf vco buf pmctl (indiv) pll divider clk_cfgx/pmctl (2xpllm) p i n m u x clkout (te s tonl) dela of 4096 clkin ccle s cclk pclk pmctl (pllbp) pmctl (2xplld) f vco f cclk f input
rev. e | page 20 of 60 | july 2009 adsp-21367/adsp-21368/adsp-21369 power-up sequencing the timing requirements for pr ocessor start-up are given in table 12 . note that during power-up, a leakage current of approximately 200a may be observed on the reset pin if it is driven low before power up is complete. this leakage current results from the weak internal pu ll-up resistor on this pin being enabled during power-up. table 12. power-up sequencing timing requirements (processor start-up) parameter min max unit timing requirements t rstvdd reset low before v ddint /v ddext on 0 ns t ivddevdd v ddint on before v ddext C50 +200 ms t clkvdd 1 clkin valid after v ddint /v ddext valid 0 200 ms t clkrst clkin valid before reset deasserted 10 2 s t pllrst pll control setup before reset deasserted 20 s switching characteristic t corerst core reset deasserted after reset deasserted 4096t ck + 2 t cclk 3, 4 1 valid v ddint /v ddext assumes that the supplies are fully ramped to their 1.2 v rails and 3.3 v rails. vo ltage ramp rates can vary from microseconds to hundreds of milliseconds depending on the de sign of the powe r supply subsystem. 2 assumes a stable clkin signal, after meeting worst-case start-up timing of crystal oscillators. refer to your crystal oscillato r manufacturers data sh eet for start-up time. assume a 25 ms maximum oscillator start-up ti me if using the xtal pin and internal osci llator circuit in conjunction with an ex ternal crystal. 3 applies after the power-up sequence is co mplete. subsequent resets require reset to be held low a minimum of four clkin cycles in order to properly initialize and propagate default states at all i/o pins. 4 the 4096 cycle count depends on t srst specification in table 14 . if setup time is not met, 1 additional clkin cycle may be added to the core reset time, resulting in 4097 cycles maximum. figure 6. power-up sequencing t rstvdd t clkvdd t clkrst t corerst t pllrst v ddext v ddint clkin clk_cfg1C0 reset resetout t ivddevdd
adsp-21367/adsp-21368/adsp-21369 rev. e | page 21 of 60 | july 2009 clock input table 13. clock input parameter 400 mhz 1 1 applies to all 40 0 mhz models. see ordering guide on page 58 . 366 mhz 2 2 applies to all 36 6 mhz models. see ordering guide on page 58 . 350 mhz 3 3 applies to all 35 0 mhz models. see ordering guide on page 58 . 333 mhz 4 4 applies to all 33 3 mhz models. see ordering guide on page 58 . 266 mhz 5 5 applies to all 26 6 mhz models. see ordering guide on page 58 . unit min max min max min max min max min max timing requirements t ck clkin period 15 6 6 applies only for clk_cfg1C0 = 00 and defa ult values for pll control bits in pmctl. 100 16.39 6 100 17.14 6 100 18 6 100 22.5 6 100 ns t ckl clkin width low 7.5 1 45 8.1 1 45 8.5 1 45 9 1 45 11.25 1 45 ns t ckh clkin width high 7.5 1 45 8.1 1 45 8.5 1 45 9 1 45 11.25 1 45 ns t ckrf clkin rise/fall (0.4 v to 2.0 v) 3 3 3 3 3ns t cclk 7 7 any changes to pll control bits in the pmctl regis ter must meet core clock timing specification t cclk . cclk period 2.5 6 10 2.73 6 10 2.85 6 10 3.0 6 10 3.75 6 10 ns f vco 8 8 see figure 5 on page 19 for vco diagram. vco frequency 100 800 100 800 100 800 100 800 100 600 mhz t ckj 9, 10 9 actual input jitter should be combined with ac specifications for acc urate timing analysis. 10 jitter specification is maximum peak-to-pe ak time interval error (tie) jitter. clkin jitter tolerance C250 +250 C250 +250 C250 +250 C250 +250 C250 +250 ps figure 7. clock input clkin t ck t ckl t ckh t ckj
rev. e | page 22 of 60 | july 2009 adsp-21367/adsp-21368/adsp-21369 clock signals the processors can use an external clock or a crystal. see the clkin pin description in table 8 on page 13 . programs can configure the processor to use its internal clock generator by connecting the necessary components to clkin and xtal. figure 8 shows the component connec tions used for a crystal operating in fundamental mode. note that the clock rate is achi eved using a 25 mhz crystal and a pll multiplier ratio 16:1 (cclk: clkin achieves a clock speed of 400 mhz). to achieve the full core clock rate, programs need to configure the multiplier bits in the pmctl register. figure 8. 400 mhz operation (fundamental mode crystal) c1 22pf y1 r1 1m * xtal clkin c2 22pf 25.00 mhz r2 47 * adsp-2136x r2 should be chosen to limit crystal drive power. refer to crystal manufacturers specifications
adsp-21367/adsp-21368/adsp-21369 rev. e | page 23 of 60 | july 2009 reset interrupts the following timing specification applies to the flag0, flag1, and flag2 pins when they are config ured as irq0 , irq1 , and irq2 interrupts. table 14. reset parameter min max unit timing requirements t wrst 1 reset pulse width low 4t ck ns t srst reset setup before clkin low 8 ns 1 applies after the power-up sequence is complete. at power-up, th e processors internal ph ase-locked loop requires no more than 1 00 s while reset is low, assuming stable v dd and clkin (not including start-up time of external clock oscillator). figure 9. reset clkin reset t srst t wrst table 15. interrupts parameter min max unit timing requirement t ipw irqx pulse width 2 t pclk +2 ns figure 10. interrupts dai_p20C1 dpi_p14C1 flag2C0 (irq2C0) t ipw
rev. e | page 24 of 60 | july 2009 adsp-21367/adsp-21368/adsp-21369 core timer the following timing specification applies to flag3 when it is configured as the core timer (tmrexp). timer pwm_out cycle timing the following timing specification applies to timer0, timer1, and timer2 in pwm_out (pulse-width modulation) mode. timer signals are routed to the dpi_p14C1 pins through the dpi sru. therefore, the timing specifications provided below are valid at the dpi_p14C1 pins. table 16. core timer parameter min max unit switching characteristic t wctim tmrexp pulse width 4 t pclk C 1 ns figure 11. core timer flag3 (tmrexp) t wctim table 17. timer pwm_out timing parameter min max unit switching characteristic t pwmo timer pulse width output 2 t pclk C 1.2 2 (2 31 C 1) t pclk ns figure 12. timer pwm_out timing dpi_p14C1 (timer2C0) t pwmo
adsp-21367/adsp-21368/adsp-21369 rev. e | page 25 of 60 | july 2009 timer wdth_cap timing the following specification ap plies to timer0, timer1, and timer2 in wdth_cap (pulse wi dth count and capture) mode. timer signals are routed to the dpi_p14C1 pins through the dpi sru. therefore, the specification provided in table 18 is valid at the dpi_p14C1 pins. pin to pin direct routing (dai and dpi) for direct pin connections only (for example, dai_pb01_i to dai_pb02_o). table 18. timer width capture timing parameter min max unit switching characteristic t pw i timer pulse width 2 t pclk 2 (2 31 C 1) t pclk ns figure 13. timer width capture timing dpi_p14C1 (timer2C0) t pwi table 19. dai/dpi pin to pin routing parameter min max unit timing requirement t dpio delay dai/dpi pin input valid to dai/dpi output valid 1.5 12 ns figure 14. dai/dpi pin to pin direct routing dai_pn dpi_pn dai_pm dpi_pm t dpio
rev. e | page 26 of 60 | july 2009 adsp-21367/adsp-21368/adsp-21369 precision clock generator (direct pin routing) this timing is only valid when the sru is configured such that the precision clock generator (pcg) takes its inputs directly from the dai pins (via pin buffers) and sends its outputs directly to the dai pins. for the other ca ses, where the pcgs inputs and outputs are not directly routed to/from dai pins (via pin buffers) there is no timing data available. all timing param- eters and switching characteristics apply to external dai pins (dai_p01C20). table 20. precision clock generator (direct pin routing) parameter min max unit timing requirement s t pcgip input clock period t pclk 4 ns t strig pcg trigger setup before falling edge of pcg input clock 4.5 ns t htrig pcg trigger hold after falling edge of pcg input clock 3ns switching characteristics t dpcgio pcg output clock and frame sync active edge delay after pcg input clock 2.5 10 ns t dtrigclk pcg output clock delay after pcg trigger 2.5 + (2.5 t pcgip ) 10 + (2.5 t pcgip )n s t dtrigfs pcg frame sync delay after pcg trigger 2.5 + ((2.5 + d C ph) t pcgip ) 10 + ((2.5 + d C ph) t pcgip )ns t pcgow 1 output clock period 2 t pcgip C 1 ns d = fsxdiv, and ph = fsxphase. for more information, see the processor hardware reference, precision clock generators chapter . 1 in normal mode. figure 15. precision clock generator (direct pin routing) dai_pn dpi_pn pcg_trigx_i dai_pm dpi_pm pcg_extx_i (clkin) dai_py dpi_py pck_clkx_o dai_pz dpi_pz pcg_fsx_o t dtrigfs t dtrigclk t dpcgio t strig t htrig t pcgow t dpcgio t pcgiw
adsp-21367/adsp-21368/adsp-21369 rev. e | page 27 of 60 | july 2009 flags the timing specifications provided below apply to the flag3C0 and dpi_p14C1 pins, and the serial peripheral interface (spi). see table 8 on page 13 for more information on flag use. table 21. flags parameter min max unit timing requirement t fipw flag3C0 in pulse width 2 t pclk + 3 ns switching characteristic t fopw flag3C0 out pulse width 2 t pclk C 1.5 ns figure 16. flags dpi_p14C1 (flag3C0 in ) (ami_data7C0) (ami_addr23C0) dpi_p14-1 (flag3C0 out ) (ami_data7C0) (ami_addr23C0) t fopw t fipw
rev. e | page 28 of 60 | july 2009 adsp-21367/adsp-21368/adsp-21369 sdram interface timing (166 mhz sdclk) the 166 mhz access speed is for a single processor. when mul- tiple adsp-21368 processors are co nnected in a shared memory system, the access speed is 100 mhz. table 22. sdram interface timing 1 366 mhz 350 mhz all other speed grades parameter min max min max min max unit timing requirement s t ssdat data setup before sdclk 500 500 500 ps t hsdat data hold after sdclk 1.23 1.23 1.23 ns switching characteristic s t sdclk sdclk period 6.83 7.14 6.0 ns t sdclkh sdclk width high 3 3 2.6 ns t sdclkl sdclk width low 3 3 2.6 ns t dcad command, addr, data delay after sdclk 2 4.8 4.8 4.8 ns t hcad command, addr, data hold after sdclk 2 1.2 1.2 1.2 ns t dsdat data disable after sdclk 5.3 5.3 5.3 ns t ensdat data enable after sdclk 1.3 1.3 1.3 ns 1 the processor needs to be programmed in t sdclk = 2.5 t cclk mode when operated at 350mhz, 366mhz and 400mhz. 2 command pins include: sdcas , sdras , sdwe , msx , sda10, sdcke. figure 17. sdram interface timing sdclk data (in) data (out) cmnd addr (out) t sdclkh t sdclkl t hsdat t ssdat t hcad t dcad t ensdat t dcad t dsdat t hcad t sdclk
adsp-21367/adsp-21368/adsp-21369 rev. e | page 29 of 60 | july 2009 sdram interface enable/disable timing (166 mhz sdclk) table 23. sdram interface enable/disable timing 1 1 for f cclk = 400 mhz (sdclk ratio = 1:2.5). parameter min max unit switching characteristics t dsdc command disable after clkin rise 2 t pclk + 3 ns t ensdc command enable after clkin rise 4.0 ns t dsdcc sdclk disable after clkin rise 8.5 ns t ensdcc sdclk enable after clkin rise 3.8 ns t dsdca address disable after clkin rise 9.2 ns t ensdca address enable after clkin rise 2 t pclk C 4 4 t pclk ns figure 18. sdram interface enable/disable timing t dsdc t dsdcc t dsdca t ensdc t ensdca t ensdcc clkin command sdclk addr command sdclk addr
rev. e | page 30 of 60 | july 2009 adsp-21367/adsp-21368/adsp-21369 memory read use these specifications for asyn chronous interfacing to memo- ries. these specifications apply when the processors are the bus master accessing external memory space in asynchronous access mode. note that timing for ack, data, rd , wr , and strobe timing parameters only apply to asynchronous access mode. table 24. memory read parameter min max unit timing requirements t dad address, selects delay to data valid 1 w + t sdclk C5.12 ns t drld rd low to data valid w C 3.2 ns t sds data setup to rd high 2.5 ns t hdrh data hold from rd high 2, 3 0n s t daak ack delay from address, selects 1, 4 t sdclk C9.5 + w ns t dsak ack delay from rd low 4 w C 7.0 ns switching characteristics t drha address selects hold after rd high rh + 0.20 ns t darl address selects to rd low 1 t sdclk C 3.3 ns t rw rd pulse width w C 1.4 ns t rwr rd high to wr , rd low hi + t sdclk C 0.8 ns w = (number of wait states specified in amictlx register) t sdclk . hi =rhc + ic (rhc = number of read hold cycles specified in amictlx register) t sdclk ic = (number of idle cycles sp ecified in amictlx register) t sdclk . h = (number of hold cycles specified in amictlx register) t sdclk . 1 the falling edge of ms x is referenced. 2 note that timing for ack, data, rd , wr , and strobe timing parameters only apply to asynchronous access mode. 3 data hold: user must meet t hda or t hdrh in asynchronous access mode. see test conditions on page 48 for the calculation of hold times given capacitive and dc loads. 4 ack delay/setup: user must meet t daak , or t dsak , for deassertion of ack (low). for asynchronou s assertion of ack (high), user must meet t daak or t dsak . figure 19. memory read ack data t drha t rw t hdrh t rwr t dad t darl t drld t sds t dsak t daak wr rd addr msx
adsp-21367/adsp-21368/adsp-21369 rev. e | page 31 of 60 | july 2009 memory write use these specifications for asyn chronous interfacing to memo- ries. these specifications apply when the processors are the bus masters, accessing external me mory space in asynchronous access mode. note that timing for ack, data, rd , wr , and strobe timing parameters only applies to asynchronous access mode. table 25. memory write parameter min max unit timing requirements t daak ack delay from address, selects 1, 2 t sdclk C 9.7 + w ns t dsak ack delay from wr low 1, 3 w C 4.9 ns switching characteristics t dawh address, selects to wr deasserted 2 t sdclk C3.1+ w ns t dawl address, selects to wr low 2 t sdclk C2.7 ns t ww wr pulse width w C 1.3 ns t ddwh data setup before wr high t sdclk C3.0+ w ns t dwha address hold after wr deasserted h + 0.15 ns t dwhd data hold after wr deasserted h + 0.02 ns t wwr wr high to wr , rd low t sdclk C1.5+ h ns t ddwr data disable before rd low 2t sdclk C 4.11 ns t wde wr low to data enabled t sdclk C 3.5 ns w = (number of wait states specified in amictlx register) t sdclk . h = (number of hold cycles specified in amictlx register) t sdclk . 1 ack delay/setup: system must meet t daak , or t dsak , for deassertion of ack (low). for asynchronou s assertion of ack (high), user must meet t daak or t dsak . 2 the falling edge of msx is referenced. 3 note that timing for ack, data, rd , wr , and strobe timing parameters only applies to asynchronous access mode. figure 20. memory write ack data t dawh t dwha t wwr t datrwh t dwhd t ww t ddwr t ddwh t dawl t wde t dsak t daak rd wr addr msx
rev. e | page 32 of 60 | july 2009 adsp-21367/adsp-21368/adsp-21369 asynchronous memory interface (ami) enable/disable use these specifications for passing bus mastership between adsp-21368 processors (brx ). table 26. ami enable/disable parameter min max unit switching characteristics t enamiac address/control enable after clock rise 4 ns t enamid data enable after clock rise t sdclk + 4 ns t disamiac address/control disable after clock rise 8.7 ns t disamid data disable after clock rise 0 ns figure 21. ami enable/disable clkin addr, wr , rd, ms1C0, data addr , wr , rd, ms1C0, data t disamiac t disamid t enamiac t enamid
adsp-21367/adsp-21368/adsp-21369 rev. e | page 33 of 60 | july 2009 shared memory bus request use these specifications for passing bus mastership between adsp-21368 processors (brx ). table 27. multiprocessor bus request parameter min max unit timing requirements t sbri brx , setup before clkin high 9 ns t hbri brx , hold after clkin high 0.5 ns switching characteristics t dbro brx delay after clkin high 9 ns t hbro brx hold after clkin high 1.0 ns figure 22. shared memory bus request t hbri t sbri t hbro t dbro clkin br x (out) br x (in)
rev. e | page 34 of 60 | july 2009 adsp-21367/adsp-21368/adsp-21369 serial ports to determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) sclk width. serial port signals sclk, frame sy nc (fs), data channel a, data channel b are routed to the dai_p20C1 pins using the sru. therefore, the timing specificatio ns provided below are valid at the dai_p20C1 pins. table 28. serial portsexternal clock 400 mhz 366 mhz 350 mhz 333 mhz 266 mhz parameter min max min max min max unit timing requirements t sfse 1 fs setup before sclk (externally generated fs in either transmit or receive mode) 2.5 2.5 2.5 ns t hfse 1 fs hold after sclk (externally generated fs in either transmit or receive mode) 2.5 2.5 2.5 ns t sdre 1 receive data setup before receive sclk 1.9 2.0 2.5 ns t hdre 1 receive data hold after sclk 2.5 2.5 2.5 ns t sclkw sclk width (t pclk 4) 2 C 0.5 (t pclk 4) 2 C 0.5 (t pclk 4) 2 C 0.5 ns t sclk sclk period t pclk 4 t pclk 4 t pclk 4 ns switching characteristics t dfse 2 fs delay after sclk (internally generated fs in either transmit or receive mode) 10.25 10.25 10.25 ns t hofse 2 fs hold after sclk (internally generated fs in either transmit or receive mode) 222ns t ddte 2 transmit data delay after transmit sclk 7.8 9.6 9.8 ns t hdte 2 transmit data hold after transmit sclk 222ns 1 referenced to sample edge. 2 referenced to drive edge.
adsp-21367/adsp-21368/adsp-21369 rev. e | page 35 of 60 | july 2009 table 29. serial portsinternal clock parameter min max unit timing requirements t sfsi 1 fs setup before sclk (externally generated fs in either transmit or receive mode) 7ns t hfsi 1 fs hold after sclk (externally generated fs in either transmit or receive mode) 2.5 ns t sdri 1 receive data setup before sclk 7 ns t hdri 1 receive data hold after sclk 2.5 ns switching characteristics t dfsi 2 fs delay after sclk (internally generated fs in transmit mode) 4 ns t hofsi 2 fs hold after sclk (internally generated fs in transmit mode) C1.0 ns t dfsir 2 fs delay after sclk (internally generated fs in receive mode) 9.75 ns t hofsir 2 fs hold after sclk (internally generated fs in receive mode) C1.0 ns t ddti 2 transmit data delay after sclk 3.25 ns t hdti 2 transmit data hold after sclk C1.0 ns t sclkiw 3 transmit or receive sclk width 2 t pclk C 1.5 2 t pclk + 1.5 ns 1 referenced to the sample edge. 2 referenced to drive edge. 3 minimum sport divisor register value. table 30. serial portsenable and three-state parameter min max unit switching characteristics t ddten 1 data enable from external transmit sclk 2 ns t ddtte 1 data disable from external transmit sclk 10 ns t ddtin 1 data enable from internal transmit sclk C1 ns 1 referenced to drive edge. table 31. serial portsexternal late frame sync parameter min max unit switching characteristics t ddtlfse 1 data delay from late external transmit fs or external receive fs with mce = 1, mfd = 0 7.75 ns t ddtenfs 1 data enable for mce = 1, mfd = 0 0.5 ns 1 the t ddtlfse and t ddtenfs parameters apply to left-justifi ed sample pair as well as dsp serial mode, and mce = 1, mfd = 0.
rev. e | page 36 of 60 | july 2009 adsp-21367/adsp-21368/adsp-21369 figure 23. external late frame sync 1 1 this figure reflects changes made to su pport left-justified sample pair mode. drive sample external receive fs with mce = 1, mfd = 0 2nd bit dai_p20C1 (sclk) dai_p20C1 (fs) dai_p20C1 (data channel a/b) 1st bit drive t ddte/i t hdte/i t ddtlfse t ddtenfs t sfse/i drive sample late external transmit fs 2nd bit dai_p20C1 (sclk) dai_p20C1 (fs) dai_p20C1 (data channel a/b) 1st bit drive t ddte/i t hdte/i t ddtlfse t ddtenfs t sfse/i t hfse/i t hfse/i notes 1. serial port signals (sclk, fs, data channel a/b) are routed to the dai_p20C1 pins using the sru. the timing specifications provided here are valid at the dai_p20C1 pins. the characterized sport ac timings are applicable when internal clocks and frames are looped back from the pin, not routed directly through the sru.
adsp-21367/adsp-21368/adsp-21369 rev. e | page 37 of 60 | july 2009 figure 24. serial ports drive edge sample edge dai_p20C1 (data channel a/b) dai_p20C1 (fs) dai_p20C1 (sclk) t hofsir t hfsi t hdri data receiveinternal clock drive edge drive edge drive edge drive edge sample edge dai_p20C1 (data channel a/b) dai_p20C1 (sclk) dai_p20C1 (data channel a/b) dai_p20C1 (fs) dai_p20C1 (sclk, ext) sclk dai_p20C1 (sclk) t hfsi t ddti data transmitinternal clock drive edge sample edge dai_p20C1 (data channel a/b) dai_p20C1 (fs) dai_p20C1 (sclk) t hofse t hofsi t hdti t hfse t hdte t ddte data transmitexternal clock drive edge sample edge dai_p20C1 (data channel a/b) dai_p20C1 (fs) dai_p20C1 (sclk) t hofse t hfse t hdre data receiveexternal clock notes 1. either the rising edge or the falling edge of sclk (external or internal) can be used as the active sampling edge. notes 1. either the rising edge or the falling edge of sclk (external or internal) can be used as the active sampling edge. t sclkiw t dfsir t sfsi t sdri t sclkw t dfse t sfse t sdre t dfse t sfse t sfsi t dfsi t sclkiw t ddtin t ddten t ddtte t sclkw
rev. e | page 38 of 60 | july 2009 adsp-21367/adsp-21368/adsp-21369 input data port the timing requirements for the idp are given in table 32 . idp signals sclk, frame sync (fs), and sdata are routed to the dai_p20C1 pins using the sru. therefore, the timing specifica- tions provided below are valid at the dai_p20C1 pins. table 32. idp parameter min max unit timing requirements t sisfs 1 fs setup before sclk rising edge 4 ns t sihfs 1 fs hold after sclk rising edge 2.5 ns t sisd 1 sdata setup before sclk rising edge 2.5 ns t sihd 1 sdata hold after sclk rising edge 2.5 ns t idpclkw clock width (t pclk 4) 2 C 1 ns t idpclk clock period t pclk 4 ns 1 data, sclk, fs can come from any of the da i pins. sclk and fs can also come via pcg or sports. pcgs input can be either clkin or any of the dai pins. figure 25. idp master timing dai_p20C1 (sclk) sample edge dai_p20C1 (fs) dai_p20C1 (sdata) t ipdclk t ipdclkw t sisfs t sihfs t sihd t sisd
adsp-21367/adsp-21368/adsp-21369 rev. e | page 39 of 60 | july 2009 parallel data acquisition port (pdap) the timing requirements for the pdap are provided in table 33 . pdap is the parallel mode operation of channel 0 of the idp. for details on the oper ation of the idp, see the idp chapter of the adsp-21368 sharc processor hardware reference . note that the 20 bits of external pdap data can be provided through the external port data31C12 pins or the dai pins. table 33. parallel data acquisition port (pdap) parameter min max unit timing requirements t spclken 1 pdap_clken setup before pdap_clk sample edge 2.5 ns t hpclken 1 pdap_clken hold after pdap_clk sample edge 2.5 ns t pdsd 1 pdap_dat setup before sclk pdap_clk sample edge 3.85 ns t pdhd 1 pdap_dat hold after sclk pdap_clk sample edge 2.5 ns t pdclkw clock width (t pclk 4) 2 C 3 ns t pdclk clock period t pclk 4 ns switching characteristics t pdhldd delay of pdap strobe after last pdap_clk capture edge for a word 2 t pclk + 3 ns t pdstrb pdap strobe pulse width 2 t pclk C 1 ns 1 data source pins are data31C12, or da i pins. source pins for sclk and fs ar e: 1) data11C10 pins, 2) dai pins. figure 26. pdap timing data dai_p20C1 (pdap_clk) sample edge dai_p20C1 (pdap_clken) dai_p20C1 (pdap_strobe) t pdstrb t pdhldd t pdhd t pdsd t spclken t hpclken t pdclk t pdclkw
rev. e | page 40 of 60 | july 2009 adsp-21367/adsp-21368/adsp-21369 pulse-width modulation generators sample rate converterserial input port the src input signals sclk, fr ame sync (fs), and sdata are routed from the dai_p20C1 pins using the sru. therefore, the timing specifications provided in table 35 are valid at the dai_p20C1 pins. table 34. pwm timing parameter min max unit switching characteristics t pwmw pwm output pulse width t pclk C 2 (2 16 C 2) t pclk C 2 ns t pwmp pwm output period 2 t pclk C 1.5 (2 16 C 1) t pclk C 1.5 ns figure 27. pwm timing pwm outputs t pwmw t pwmp table 35. src, serial input port parameter min max unit timing requirements t srcsfs 1 fs setup before sclk rising edge 4 ns t srchfs 1 fs hold after sclk rising edge 5.5 ns t srcsd 1 sdata setup before sclk rising edge 4 ns t srchd 1 sdata hold after sclk rising edge 5.5 ns t srcclkw clock width (t pclk 4) 2 C 1 ns t srcclk clock period t pclk 4 ns 1 data, sclk, fs can come from any of the da i pins. sclk and fs can also come via pcg or sports. pcgs input can be either clkin or any of the dai pins. figure 28. src serial input port timing dai_p20C1 (sclk) sample edge dai_p20C1 (fs) dai_p20C1 (sdata) t srcclk t srcclkw t srcsfs t srchfs t srchd t srcsd
adsp-21367/adsp-21368/adsp-21369 rev. e | page 41 of 60 | july 2009 sample rate converterserial output port for the serial output port, the frame-sync is an input and it should meet setup and hold times with regard to sclk on the output port. the serial data output, sdata, has a hold time and delay specification with regard to sclk. note that sclk rising edge is the sampling ed ge and the falling edge is the drive edge. table 36. src, serial output port parameter min max unit timing requirements t srcsfs 1 fs setup before sclk rising edge 4 ns t srchfs 1 fs hold after sclk rising edge 5.5 ns t srcclkw clock width (t pclk 4) 2 C 1 ns t srcclk clock period t pclk 4 ns switching characteristics t srctdd 1 transmit data delay after sclk falling edge 9.9 ns t srctdh 1 transmit data hold after sclk falling edge 1 ns 1 data, sclk, and fs can come from any of the dai pins. sclk and fs can also come via pcg or spor ts. pcgs input can be either c lkin or any of the dai pins. figure 29. src serial output port timing dai_p20C1 (sclk) sample edge dai_p20C1 (fs) dai_p20C1 (sdata) t srcclk t srcclkw t srcsfs t srchfs t srctdd t srctdh
rev. e | page 42 of 60 | july 2009 adsp-21367/adsp-21368/adsp-21369 s/pdif transmitter serial data input to the s/pdif transmitter can be formatted as left justified, i 2 s, or right justified with word widths of 16, 18, 20, or 24 bits. the following sect ions provide timing for the transmitter. s/pdif transmitterserial input waveforms figure 30 shows the right-ju stified mode. lrclk is high for the left channel and low for the right channel. data is valid on the rising edge of sclk. the msb is delayed 12-bit clock periods (in 20-bit output mode) or 16-bit clock periods (in 16-bit output mode) from an lrclk transition, so that when there are 64 sclk periods per lrclk period, the lsb of the data is right- justified to the next lrclk transition. figure 31 shows the default i 2 s-justified mode. lrclk is low for the left channel and high for the right channel. data is valid on the rising edge of sclk. th e msb is left-justified to an lrclk transition but with a single sclk period delay. figure 32 shows the left-justified mo de. lrclk is high for the left channel and low fo r the right channel. data is valid on the rising edge of sclk. the msb is left-justified to an lrclk transition with no msb delay. figure 30. right-justified mode msb left channel right channel lsb lsb msb C 1 msb C 2 msb msb C 1 msb C 2 lsb + 2 lsb + 1 lsb lsb + 2 lsb + 1 dai_p20C1 lrclk dai_p20C1 sclk dai_p20C1 sdata figure 31. i 2 s-justified mode left channel right channel lsb msb C 1 msb C 2 lsb + 2 lsb + 1 msbm sb lsb msb C 1 msb C 2 lsb + 2 lsb + 1 dai_p20C1 lrclk dai_p20C1 sclk dai_p20C1 sdata msb figure 32. left-justified mode left channel right channel msb lsb msb C 1 msb C 2 msb msb C 1 msb msb + 1 msb C 2 lsb + 2 lsb + 1 lsb lsb + 2 lsb + 1 dai_p20C1 lrclk dai_p20C1 sclk dai_p20C1 sdata
adsp-21367/adsp-21368/adsp-21369 rev. e | page 43 of 60 | july 2009 s/pdif transmitter input data timing the timing requirements for the input port are given in table 37 . input signals sclk, frame sync (fs), and sdata are routed to the dai_p20C1 pins using the sru. therefore, the timing specifications provided below are valid at the dai_p20C1 pins. oversampling clock (txclk) switching characteristics the s/pdif transmitter has an ov ersampling clock. this txclk input is divided down to generate the biphase clock. table 37. s/pdif transmitter input data timing parameter min max unit timing requirements t sisfs 1 fs setup before sclk rising edge 3 ns t sihfs 1 fs hold after sclk rising edge 3 ns t sisd 1 sdata setup before sclk rising edge 3 ns t sihd 1 sdata hold after sclk rising edge 3 ns t sisclkw clock width 36 ns t sisclk clock period 80 ns t sitxclkw transmit clock width 9 ns t sitxclk transmit clock period 20 ns 1 data, sclk, and fs can come from any of the dai pins. sclk and fs can also come via pcg or spor ts. pcgs input can be either c lkin or any of the dai pins. figure 33. s/pdif transmitter input timing sample edge dai_p20C1 (txclk) dai_p20C1 (sclk) dai_p20C1 (fs) dai_p20C1 (sdata) t sitxclkw t sitxclk t sisclkw t sisclk t sisfs t sihfs t sisd t sihd table 38. oversampling clock (txc lk) switching characteristics parameter min max unit txclk frequency for txclk = 384 fs oversampling ratio fs <= 1/t sitxclk mhz txclk frequency for txclk = 256 fs 49.2 mhz frame rate (fs) 192.0 khz
rev. e | page 44 of 60 | july 2009 adsp-21367/adsp-21368/adsp-21369 s/pdif receiver the following section describes timing as it relates to the s/pdif receiver. internal digital pll mode in the internal digital phase-lock ed loop mode the internal pll (digital pll) generates the 512 fs clock. table 39. s/pdif receiver inte rnal digital pll mode timing parameter min max unit switching characteristics t dfsi lrclk delay after sclk 5 ns t hofsi lrclk hold after sclk C2 ns t ddti transmit data delay after sclk 5 ns t hdti transmit data hold after sclk C2 ns t sclkiw 1 transmit sclk width 40 ns 1 sclk frequency is 64 fs where fs = the frequency of lrclk. figure 34. s/pdif receiver internal digital pll mode timing dai_p20C1 (sclk) sample edge dai_p20C1 (fs) dai_p20C1 (data channel a/b) drive edge t sclkiw t dfsi t hofsi t ddti t hdti
adsp-21367/adsp-21368/adsp-21369 rev. e | page 45 of 60 | july 2009 spi interfacemaster the processors contain two spi ports. the primary has dedi- cated pins and the secondary is available through the dpi. the timing provided in table 40 and table 41 on page 46 applies to both. table 40. spi interface protocolmaster switching and timing specifications parameter min max unit timing requirements t sspidm data input valid to spiclk edge (data input setup time) 8.2 ns t hspidm spiclk last sampling edge to data input not valid 2 ns switching characteristics t spiclkm serial clock cycle 8 t pclk C 2 ns t spichm serial clock high period 4 t pclk C 2 ns t spiclm serial clock low period 4 t pclk C 2 ns t ddspidm spiclk edge to data out valid (data out delay time) 2.5 ns t hdspidm spiclk edge to data out not valid (data out hold time) 4 t pclk C 2 ns t sdscim flag3C0in (spi device select) low to first spiclk edge 4 t pclk C 2 ns t hdsm last spiclk edge to flag3C0in high 4 t pclk C 2 ns t spitdm sequential transfer delay 4 t pclk C 1 ns figure 35. spi master timing t spichm t sdscim t spiclm t spiclkm t hdsm t spitdm t spiclm t spichm msb valid lsb valid msb valid lsb lsb msb msb t ddspidm t hspidm t sspidm lsb valid flag3C0 (output) spiclk (cp = 0) (output) spiclk (cp = 1) (output) mosi (output) miso (input) mosi (output) miso (input) cphase = 1 cphase = 0 t hdspidm t hspidm t hspidm t sspidm t sspidm t ddspidm t hdspidm
rev. e | page 46 of 60 | july 2009 adsp-21367/adsp-21368/adsp-21369 spi interfaceslave table 41. spi interface protocolslave switching and timing specifications parameter min max unit timing requirements t spiclks serial clock cycle 4 t pclk C 2 ns t spichs serial clock high period 2 t pclk C 2 ns t spicls serial clock low period 2 t pclk C 2 ns t sdsco spids assertion to first spiclk edge, cphase = 0 or cphase = 1 2 t pclk ns t hds last spiclk edge to spids not asserted, cphase = 0 2 t pclk ns t sspids data input valid to spiclk edge (data input setup time) 2 ns t hspids spiclk last sampling edge to data input not valid 2 ns t sdppw spids deassertion pulse width (cphase = 0) 2 t pclk ns switching characteristics t dsoe spids assertion to data out active 0 6.8 ns t dsoe 1 spids assertion to data out active (spi2) 0 8 ns t dsdhi spids deassertion to data high impedance 0 6.8 ns t dsdhi 1 spids deassertion to data high impedance (spi2) 0 8.6 ns t ddspids spiclk edge to data out valid (data out delay time) 9.5 ns t hdspids spiclk edge to data out not valid (data out hold time) 2 t pclk ns t dsov spids assertion to data out valid (cphase = 0) 5 t pclk ns 1 the timing for these parameters applies when the spi is routed through the signal ro uting unit. for more information, see the processor hardware refere nce, serial peripheral interface port chapter. figure 36. spi slave timing t spichs t spicls t spiclks t hds t sdppw t sdsco t spicls t spichs t dsoe t ddspids t ddspids t dsdhi t hdspids t hspids t sspids msb valid lsb valid msb valid t sspids lsb lsb msb msb t dsdhi t ddspids t dsov t hspids t sspids t hdspids lsb valid spids (input) spiclk (cp = 0) (input) spiclk (cp = 1) (input) miso (output) mosi (input) miso (output) mosi (input) cphase = 1 cphase = 0
adsp-21367/adsp-21368/adsp-21369 rev. e | page 47 of 60 | july 2009 jtag test access port and emulation table 42. jtag test access port and emulation parameter min max unit timing requirements t tck tck period t ck ns t stap tdi, tms setup before tck high 5 ns t htap tdi, tms hold after tck high 6 ns t ssys 1 system inputs setup before tck high 7 ns t hsys 1 system inputs hold after tck high 18 ns t trstw trst pulse width 4t ck ns switching characteristics t dtdo tdo delay from tck low 7 ns t dsys 2 system outputs delay after tck low t ck 2 + 7 ns 1 system inputs = ad15C0, spids , clk_cfg1C0, reset , boot_cfg1C0, miso, mosi, spiclk, dai_px, flag3C0. 2 system outputs = miso, mosi, spiclk, dai_px, ad15C0, rd , wr , flag3C0, emu . figure 37. ieee 1149.1 jtag test access port tck tms tdi tdo system inputs system outputs t tck t stap t htap t dtdo t ssys t hsys t dsys
rev. e | page 48 of 60 | july 2009 adsp-21367/adsp-21368/adsp-21369 output drive currents figure 38 shows typical i-v characteri stics for the output driv- ers and figure 39 shows typical i-v characteristics for the sdclk output drivers. the curves represent the current drive capability of the output drivers as a function of output voltage. test conditions the ac signal specifications (timing parameters) appear in table 14 on page 23 through table 42 on page 47 . these include output disable time, output enable time, and capacitive loading. the timing specifications for the sharc apply for the voltage reference levels in figure 40 . timing is measured on signals wh en they cross the 1.5 v level as described in figure 40 . all delays (in nanoseconds) are mea- sured between the point that the first signal reaches 1.5 v and the point that the second signal reaches 1.5 v. capacitive loading output delays and holds are based on standard capacitive loads of an average of 6 pf on all pins (see figure 41 ). figure 46 and figure 47 show graphically how outp ut delays and holds vary with load capacitance. the graphs of figure 42 through figure 47 may not be linear outside the ranges shown for typi- cal output delay vs. load capaci tance and typical output rise time (20% to 80%, v = mi n) vs. load capacitance. figure 38. typical drive at junction temperature figure 39. sdclk1C0 drive at junction temperature s weep (v ddext ) voltage (v) - 20 0 3 .5 0.5 1.0 1.5 2.0 2.5 3 .0 0 - 40 - 3 0 20 40 - 10 s o u r c e ( v d d e x t ) c u r r e n t ( m a ) v ol 3 .11v, 125c 3 . 3 v, 25c 3 .47v, - 45c v oh 3 0 10 3 .11v, 125c 3 . 3 v, 25c 3 .47v, - 45c 3 .11v, 105c 3 .11v, 105c - 60 0 3 .5 0.5 1.0 1.5 2.0 2.5 3 .0 0 - 45 - 3 0 60 75 - 15 s o u r c e ( v d d e x t ) c u r r e n t ( m a ) v ol 3 .1 3 v, 1 2 5 c 3 . 3 v, 2 5 c 3 .47v, - 45c v oh 3 .1 3 v, 1 05 c 45 - 90 - 75 - 105 3 0 15 3 .1 3 v, 1 25 c 3 . 3 v, 2 5 c 3 .47v, - 45c 3 .1 3 v, 1 0 5 c s weep (v ddext )voltage(v) figure 40. voltage reference levels for ac measurements figure 41. equivalent device loading for ac measurements (includes all fixtures) input or output 1.5v 1.5v t1 zo = 50:(impedance) td = 4.04 r 1.18 ns 2pf tester pin electronics 50 : 0.5pf 70 : 400 : 45 : 4pf notes: the worst case transmission line delay is shown and can be used for the output timing analysis to refelect the transmission line effect and must be considered. the transmission line (td), is for load only and does not affect the data sheet timing specifications. analog devices recommends using the ibis model timing for a given system requirement. if necessary, a system may incorporate external drivers to compensate for any timing differences. 1.5v dut output
adsp-21367/adsp-21368/adsp-21369 rev. e | page 49 of 60 | july 2009 figure 42. typical outp ut rise/fall time (20% to 80%, v ddext = min) figure 43. typical outp ut rise/fall time (20% to 80%, v ddext = max) load capacitance (pf) 12 0 50 100 150 200 250 10 8 6 4 r i s e a n d f a l l t i m e s ( n s ) 2 0 ri s e fall y = 0.049x + 1.5105 y=0.04 8 2x + 1.4604 load capacitance (pf) 8 0 0 100 250 12 4 2 10 6 r i s e a n d f a l l t i m e s ( n s ) 200 150 50 fall y = 0.0467x + 1.6 3 2 3 y = 0.045x + 1.524 ris e figure 44. sdclk typical output rise/fall time (20% to 80%, v ddext = min) figure 45. sdclk typical output rise/fall time (20% to 80%, v ddext = max) load capacitance (pf) 0 50 100 150 200 250 10 8 6 4 r i s e a n d f a l l t i m e s ( n s ) 2 0 ris e fall y=0.0 3 72x + 0.22 8 y = 0.0277x + 0. 3 69 load capacitance (pf) 0 50 100 150 200 250 10 8 6 4 r i s e a n d f a l l t i m e s ( n s ) 2 0 ris e fall y=0.0 3 64x + 0.197 y = 0.0259x + 0. 3 11
rev. e | page 50 of 60 | july 2009 adsp-21367/adsp-21368/adsp-21369 thermal characteristics the adsp-21367/adsp-21368/adsp -21369 processors are rated for performance over the temperature range specified in operating conditions on page 16 . table 43 and table 44 airflow measurements comply with jedec standards jesd51-2 and jesd51-6 and the junction-to- board measurement complies with jesd51-8. test board design complies with jedec standards jesd51-9 (bga_ed) and jesd51-8 (lqfp_ep). the juncti on-to-case measurement com- plies with mil-std-883. all measurements use a 2s2p jedec test board. the lqfp-ep package requires th ermal trace squares and ther- mal vias, to an embedded ground plane, in the pcb. refer to jedec standard jesd51-5 for more information. to determine the junction temperature of the device while on the application pcb, use: where: t j = junction temperature ( c) t top = case temperature ( c) measured at the top center of the package jt = junction-to-top (of package) characterization parameter is the typical value from table 43 and table 44 . p d = power dissipation (see ee note ee-299) values of ja are provided for package comparison and pcb design considerations. ja can be used for a first-order approxi- mation of t j by the equation: where: t a = ambient temperature ( c) values of jc are provided for package comparison and pcb design considerations when an external heat sink is required. this is only applicable when a heat sink is used. values of jb are provided for package comparison and pcb design considerations. the ther mal characteristics values pro- vided in table 43 and table 44 are modeled values @ 2 w. figure 46. typical output delay or hold vs. load capacitance (at junction temperature) figure 47. sdclk typical output delay or hold vs. load capacitance (at junction temperature) load capacitance (pf) 0 200 50 100 150 10 8 o u t p u t d e l a y o r h o l d ( n s ) - 4 6 0 4 2 - 2 y = 0.04 88x - 1.592 3 load capacitance ( p f ) 6 - 2 0100 2 0 8 4 r i s e a n d f a l l t i m e s ( n s ) 200 150 50 y = 0.0256x - 0.021 table 43. thermal characteristics for 256-ball bga_ed parameter condition typical unit ja airflow = 0 m/s 12.5 c/w jma airflow = 1 m/s 10.6 c/w jma airflow = 2 m/s 9.9 c/w jc 0.7 c/w jb 5.3 c/w jt airflow = 0 m/s 0.3 c/w jmt airflow = 1 m/s 0.3 c/w jmt airflow = 2 m/s 0.3 c/w table 44. thermal characteristics for 208-lead lqfp epad (with exposed pad soldered to pcb) parameter condition typical unit ja airflow = 0 m/s 17.1 c/w jma airflow = 1 m/s 14.7 c/w jma airflow = 2 m/s 14.0 c/w jc 9.6 c/w jt airflow = 0 m/s 0.23 c/w jmt airflow = 1 m/s 0.39 c/w jmt airflow = 2 m/s 0.45 c/w jb airflow = 0 m/s 11.5 c/w jmb airflow = 1 m/s 11.2 c/w jmb airflow = 2 m/s 11.0 c/w t j t top jt p d () += t j t a ja p d () +=
adsp-21367/adsp-21368/adsp-21369 rev. e | page 51 of 60 | july 2009 256-ball bga_ed pinout the following table shows th e adsp-2136xs pin names and their default function after reset (in parentheses). table 45. 256-ball bga_ed pin assignment (numerically by ball number) ball no. signal ball no. signal ball no. signal ball no. signal a01 nc b01 dai_p05 (sd1a) c01 dai_p09 (sd2a) d01 dai_p10 (sd2b) a02 tdi b02 sdclk1 1 c02 dai_p07 (sclk1) d02 dai_p06 (sd1b) a03 tms b03 trst c03 gnd d03 gnd a04 clk_cfg0 b04 tck c04 v ddext d04 v ddext a05 clk_cfg1 b05 boot_cfg0 c05 gnd d05 gnd a06 emu b06 boot_cfg1 c06 gnd d06 v ddext a07 dai_p04 (sfs0) b07 tdo c07 v ddint d07 v ddint a08 dai_p01 (sd0a) b08 dai_p03 (sclk0) c08 gnd d08 gnd a09 dpi_p14 (timer1) b09 dai_p02 (sd0b) c09 gnd d09 v ddext a10 dpi_p12 (twi_clk) b10 dpi_p13 (timer0) c10 v ddint d10 v ddint a11 dpi_p10 (uart0rx) b11 dpi_p11 (twi_data) c11 gnd d11 gnd a12 dpi_p09 (uart0tx) b12 dpi_p08 (spiflg3) c12 gnd d12 v ddext a13 dpi_p07 (spiflg2) b13 dpi_p05 (spiflg0) c13 v ddint d13 v ddint a14 dpi_p06 (spiflg1) b14 dpi_p04 (spids) c14 gnd d14 gnd a15 dpi_p03 (spiclk) b15 dpi_p01 (spimosi) c15 gnd d15 v ddext a16 dpi_p02 (spimiso) b16 reset c16 v ddint d16 gnd a17 resetout b17 data30 c17 v ddint d17 v ddext a18 data31 b18 data29 c18 v ddint d18 gnd a19 nc b19 data28 c19 data27 d19 data26 a20 nc b20 nc c20 nc/rpba 2 d20 data24 e01 dai_p11 (sd3a) f01 dai_p14 (sfs3) g01 dai_p15 (sd4a) h01 dai_p17 (sd5a) e02 dai_p08 (sfs1) f02 dai_p12 (sd3b) g02 dai_p13 (sclk3) h02 dai_p16 (sd4b) e03 v ddint f03 gnd g03 gnd h03 v ddint e04 v ddint f04 gnd g04 v ddext h04 v ddint e17 gnd f17 v ddext g17 v ddint h17 v ddext e18 gnd f18 gnd g18 v ddint h18 gnd e19 data25 f19 gnd/id2 2 g19 data22 h19 data19 e20 data23 f20 data21 g20 data20 h20 data18 j01 dai_p19 (sclk5) k01 flag0 l01 flag2 m01 ack j02 dai_p18 (sd5b) k02 dai_p20 (sfs5) l02 flag1 m02 flag3 j03 gnd k03 gnd l03 v ddint m03 gnd j04 gnd k04 v ddext l04 v ddint m04 gnd j17 gnd k17 v ddint l17 v ddint m17 v ddext j18 gnd k18 v ddint l18 v ddint m18 gnd j19 gnd/id1 2 k19 gnd/id0 2 l19 data15 m19 data12 j20 data17 k20 data16 l20 data14 m20 data13
rev. e | page 52 of 60 | july 2009 adsp-21367/adsp-21368/adsp-21369 n01 rd p01 sda10 r01 sdwe t01 sdcke n02 sdclk0 p02 wr r02 sdras t02 sdcas n03 gnd p03 v ddint r03 gnd t03 gnd n04 v ddext p04 v ddint r04 gnd t04 v ddext n17 gnd p17 v ddint r17 v ddext t17 gnd n18 gnd p18 v ddint r18 gnd t18 gnd n19 data11 p19 data8 r19 data6 t19 data5 n20 data10 p20 data9 r20 data7 t20 data4 u01 ms0 v01 addr22 w01 gnd y01 gnd u02 ms1 v02 addr23 w02 addr21 y02 nc u03 v ddint v03 v ddint w03 addr19 y03 nc u04 gnd v04 gnd w04 addr20 y04 addr18 u05 v ddext v05 gnd w05 addr17 y05 nc/br1 2 u06 gnd v06 gnd w06 addr16 y06 nc/br2 2 u07 v ddext v07 gnd w07 addr15 y07 xtal u08 v ddint v08 v ddint w08 addr14 y08 clkin u09 v ddext v09 gnd w09 a vdd y09 nc u10 gnd v10 gnd w10 a vss y10 nc u11 v ddext v11 gnd w11 addr13 y11 nc/br3 2 u12 v ddint v12 v ddint w12 addr12 y12 nc/br4 2 u13 v ddext v13 v ddext w13 addr10 y13 addr11 u14 v ddext v14 gnd w14 addr8 y14 addr9 u15 v ddint v15 v ddint w15 addr5 y15 addr7 u16 v ddext v16 gnd w16 addr4 y16 addr6 u17 v ddint v17 gnd w17 addr1 y17 addr3 u18 v ddint v18 gnd w18 addr2 y18 gnd u19 data0 v19 data1 w19 addr0 y19 gnd u20 data2 v20 data3 w20 nc y20 nc 1 the sdclk1 signal is only available on the sbga package. sdclk1 is not available on the lqfp_ep package. 2 applies to adsp-21368 models only. table 45. 256-ball bga_ed pin assignment (n umerically by ball number) (continued) ball no. signal ball no. signal ball no. signal ball no. signal
adsp-21367/adsp-21368/adsp-21369 rev. e | page 53 of 60 | july 2009 figure 48 shows the bottom view of the bga_ed ball configu- ration. figure 49 shows the top view of the bga_ed ball configuration. figure 48. 256-ball bga_ed ball configuration (bottom view) 1 2 3 4 5 6 7 8 9 10 11 12 14 15 1 3 16 17 19 20 1 8 r p n m l k j h g f e d c b a y w v u t no connect v ddint i/o s ignal s gnd key v ddext a v ss a vdd bottom view figure 49. 256-ball bga_ed ball configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 14 15 1 3 16 17 19 20 1 8 r p n m l k j h g f e d c b a y w v u t no connect v ddint i/o s ignal s gnd key v ddext a v ss a vdd top view
rev. e | page 54 of 60 | july 2009 adsp-21367/adsp-21368/adsp-21369 208-lead lqfp_ep pinout the following table shows th e adsp-2136xs pin names and their default function after reset (in parentheses). table 46. 208-lead lqfp_ep pin assignme nt (numerically by lead number) lead no. signal lead no. signal lead no. signal lead no. signal lead no. signal 1v ddint 43 v ddint 85 v ddext 127 v ddint 169 clk_cfg0 2 data28 44 data4 86 gnd 128 gnd 170 boot_cfg0 3 data27 45 data5 87 v ddint 129 v ddext 171 clk_cfg1 4 gnd 46 data2 88 addr14 130 dai_p19 (sclk5) 172 emu 5v ddext 47 data3 89 gnd 131 dai_p18 (sd5b) 173 boot_cfg1 6 data26 48 data0 90 v ddext 132 dai_p17 (sd5a) 174 tdo 7 data25 49 data1 91 addr15 133 dai_p16 (sd4b) 175 dai_p04 (sfs0) 8data24 50 v ddext 92 addr16 134 dai_p15 (sd4a) 176 dai_p02 (sd0b) 9 data23 51 gnd 93 addr17 135 dai_p14 (sfs3) 177 dai_p03 (sclk0) 10 gnd 52 v ddint 94 addr18 136 dai_p13 (sclk3) 178 dai_p01 (sd0a) 11 v ddint 53 v ddint 95 gnd 137 dai_p12 (sd3b) 179 v ddext 12 data22 54 gnd 96 v ddext 138 v ddint 180 gnd 13 data21 55 v ddext 97 addr19 139 v ddext 181 v ddint 14 data20 56 addr0 98 addr20 140 gnd 182 gnd 15 v ddext 57 addr2 99 addr21 141 v ddint 183 dpi_p14 (timer1) 16 gnd 58 addr1 100 addr23 142 gnd 184 dpi_p13 (timer0) 17 data19 59 addr4 101 addr22 143 dai_p11 (sd3a) 185 dpi_p12 (twi_clk) 18 data18 60 addr3 102 ms1 144 dai_p10 (sd2b) 186 dpi_p11 (twi_data) 19 v ddint 61 addr5 103 ms0 145 dai_p08 (sfs1) 187 dpi_p10 (uart0rx) 20 gnd 62 gnd 104 v ddint 146 dai_p09 (sd2a) 188 dpi_p09 (uart0tx) 21 data17 63 v ddint 105 v ddint 147 dai_p06 (sd1b) 189 dpi_p08 (spiflg3) 22 v ddint 64 gnd 106 gnd 148 dai_p07 (sclk1) 190 dpi_p07 (spiflg2) 23 gnd 65 v ddext 107 v ddext 149 dai_p05 (sd1a) 191 v ddext 24 v ddint 66 addr6 108 sdcas 150 v ddext 192 gnd 25 gnd 67 addr7 109 sdras 151 gnd 193 v ddint 26 data16 68 addr8 110 sdcke 152 v ddint 194 gnd 27 data15 69 addr9 111 sdwe 153 gnd 195 dpi_p06 (spiflg1) 28 data14 70 addr10 112 wr 154 v ddint 196 dpi_p05 (spiflg0) 29 data13 71 gnd 113 sda10 155 gnd 197 dpi_p04 (spids) 30 data12 72 v ddint 114 gnd 156 v ddint 198 dpi_p03 (spiclk) 31 v ddext 73 gnd 115 v ddext 157 v ddint 199 dpi_p01 (spimosi) 32 gnd 74 v ddext 116 sdclk0 158 v ddint 200 dpi_p02 (spimiso) 33 v ddint 75 addr11 117 gnd 159 gnd 201 resetout 34 gnd 76 addr12 118 v ddint 160 v ddint 202 reset 35 data11 77 addr13 119 rd 161 v ddint 203 v ddext 36 data10 78 gnd 120 ack 162 v ddint 204 gnd 37 data9 79 v ddint 121 flag3 163 tdi 205 data30 38 data8 80 a vss 122 flag2 164 trst 206 data31 39 data7 81 a vdd 123 flag1 165 tck 207 data29
adsp-21367/adsp-21368/adsp-21369 rev. e | page 55 of 60 | july 2009 40 data6 82 gnd 124 flag0 166 gnd 208 v ddint 41 v ddext 83 clkin 125 dai_p20 (sfs5) 167 v ddint 42 gnd 84 xtal 126 gnd 168 tms table 46. 208-lead lqfp_ep pin assignment (n umerically by lead number) (continued) lead no. signal lead no. signal lead no. signal lead no. signal lead no. signal
rev. e | page 56 of 60 | july 2009 adsp-21367/adsp-21368/adsp-21369 package dimensions the adsp-21367/adsp-21368/adsp -21369 processors are available in 256-ball rohs co mpliant and leaded bga_ed, and 208-lead rohs compliant lqfp_ep packages. figure 50. 208-lead low profile quad flat package, exposed pad [lqfp_ep] (sw-208-1) dimensions shown in millimeters complia nt to jedec st andards ms-026-bjb-hd 100907a 0.15 0.10 0.05 0.08 coplanarity 0.20 0.15 0.09 1.45 1.40 1.35 7 3.5 0 view a rot a ted 90 ccw 0.27 0.22 0.17 0.75 0.60 0.45 0.50 bsc lead pitch 28.10 28.00 sq 27.90 30.20 30.00 sq 29.80 top vie w ( pins dow n ) b otto m view ( pins up) exposed p ad 1 52 53 52 53 105 104 105 104 156 208 1 208 157 156 157 pin 1 1.60 max 1.00 ref sea ting plane view a 8.890 ref 8.712 ref 25.50 ref note: the exposed pad is required to be electrically and thermally connected to vss. this should be implemented by soldering the exposed pad to a vss pcb land that is the same size as the exposed pad. the vss pcb land should be robustly connected to the vss plane in the pcb with an array of thermal vias for best performance.
adsp-21367/adsp-21368/adsp-21369 rev. e | page 57 of 60 | july 2009 surface-mount design table 47 is provided as an aide to pcb design. for industry- standard design recommendations, refer to ipc-7351, generic requirements for surface-mount design and land pattern standard . figure 51. 256-ball ball grid a rray, thermally enhanced [bga_ed] (bp-256) dimension shown in millimeters complia nt to jedec standards mo-192-bal-2 0.10 min 0.70 0.60 0.50 1.00 0.80 0.60 coplanarity 0.20 0.90 0.75 0.60 seating plane ball diameter 0 .25 m in (4 ) detail a 1.70 max 1.27 bsc a b c d e f g h j k l m n p r t u v w y 1 3 5 7 9 11 1 3 1 5 1 9 2 4 68 10 1 2 1 4 1 6 1 82 0 24.13 bsc sq bottom view a1 corner index area top vie w 27.00 bsc sq ball a1 indicator detail a 1 7 table 47. bga_ed data for use with surface-mount design package ball attach type solder mask opening ball pad size 256-lead ball grid array bga_ed (bp-256) solder mask defined (smd) 0.63 mm 0.73 mm
rev. e | page 58 of 60 | july 2009 adsp-21367/adsp-21368/adsp-21369 automotive products an adsp-21369 model is available for automotive applications with controlled manufacturing. note that this special model may have specifications that differ from the general release models. the automotive grade product shown in table 48 is available for use in automotive applications. contact your local adi account representative or authorized adi product distributor for spe- cific product ordering informatio n. note that all automotive products are rohs compliant. ordering guide table 48. automotive products model temperature range 1 instruction rate on-chip sram rom package description package option ad21369wbswz1xx C40c to +85c 266 mhz 2m bit 6m bit 208-lead lqfp_ep sw-208-1 1 referenced temperature is ambient temperature. model temperature range 1 1 referenced temperature is ambient temperature. instruction rate on-chip sram rom package description package option adsp-21367kbp-2a 2 2 available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. fo r a complete list, visit our website at www.analog.com/sharc. 0c to +70c 333 mhz 2m bi t 6m bit 256-ball bga_ed bp-256 adsp-21367kbpz-2a 2, 3 3 z = rohs compliant part. 0c to +70c 333 mhz 2m bi t 6m bit 256-ball bga_ed bp-256 adsp-21367bbp-2a 2 C40c to +85c 333 mhz 2m bit 6m bit 256-ball bga_ed bp-256 adsp-21367bbpz-2a 2, 3 C40c to +85c 333 mhz 2m bit 6m bit 256-ball bga_ed bp-256 adsp-21367kbpz-3a 2, 3 0c to +70c 400 mhz 2m bi t 6m bit 256-ball bga_ed bp-256 adsp-21367kswz-1a 2, 3 0c to +70c 266 mhz 2m bit 6m bit 208-lead lqfp_ep sw-208-1 adsp-21367kswz-2a 2, 3 0c to +70c 333 mhz 2m bit 6m bit 208-lead lqfp_ep sw-208-1 adsp-21367kswz-4a 2, 3 0c to +70c 350 mhz 2m bit 6m bit 208-lead lqfp_ep sw-208-1 adsp-21367kswz-5a 2, 3 0c to +70c 366 mhz 2m bit 6m bit 208-lead lqfp_ep sw-208-1 adsp-21367bswz-1a 2, 3 C40c to +85c 266 mhz 2m bit 6m bit 208-lead lqfp_ep sw-208-1 adsp-21368kbp-2a 0c to +70c 333 mhz 2m bit 6m bit 256-ball bga_ed bp-256 adsp-21368kbpz-2a 3 0c to +70c 333 mhz 2m bi t 6m bit 256-ball bga_ed bp-256 adsp-21368bbp-2a C40c to +85c 333 mhz 2m bit 6m bit 256-ball bga_ed bp-256 adsp-21368bbpz-2a 3 C40c to +85c 333 mhz 2m bit 6m bit 256-ball bga_ed bp-256 adsp-21368kbpz-3a 3 0c to +70c 400 mhz 2m bi t 6m bit 256-ball bga_ed bp-256 adsp-21369kbp-2a 0c to +70c 333 mhz 2m bit 6m bit 256-ball bga_ed bp-256 adsp-21369kbpz-2a 3 0c to +70c 333 mhz 2m bi t 6m bit 256-ball bga_ed bp-256 ADSP-21369BBP-2A C40c to +85c 333 mhz 2m bit 6m bit 256-ball bga_ed bp-256 adsp-21369bbpz-2a 2 C40c to +85c 333 mhz 2m bit 6m bit 256-ball bga_ed bp-256 adsp-21369kbpz-3a 3 0c to +70c 400 mhz 2m bi t 6m bit 256-ball bga_ed bp-256 adsp-21369kswz-1a 3 0c to +70c 266 mhz 2m bit 6m bit 208-lead lqfp_ep sw-208-1 adsp-21369kswz-2a 3 0c to +70c 333 mhz 2m bit 6m bit 208-lead lqfp_ep sw-208-1 adsp-21369kswz-4a 3 0c to +70c 350 mhz 2m bit 6m bit 208-lead lqfp_ep sw-208-1 adsp-21369kswz-5a 3 0c to +70c 366 mhz 2m bit 6m bit 208-lead lqfp_ep sw-208-1 adsp-21369bswz-1a 3 C40c to +85c 266 mhz 2m bit 6m bit 208-lead lqfp_ep sw-208-1 adsp-21369bswz-2a 3 C40c to +85c 333 mhz 2m bit 6m bit 208-lead lqfp_ep sw-208-1
adsp-21367/adsp-21368/adsp-21369 rev. e | page 59 of 60 | july 2009
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